參數(shù)資料
型號(hào)： NCP5218
廠商： ON SEMICONDUCTOR
英文描述： 2−in−1 Notebook DDR Power Controller
文件頁數(shù)： 27/31頁
文件大小： 463K
代理商： NCP5218
NCP5218
http://onsemi.com
27
PCB Layout Guidelines
Cautious PCB layout design is very critical to ensure
high performance and stable operation of the DDR power
controller. The following items must be considered when
preparing PCB layout:
1. All high
current traces must be kept as short and
wide as possible to reduce power loss.
High
current traces are the trace from the input
voltage terminal to the drain of the high
side
MOSFET, the trace from the source of the
high
side MOSFET to the inductor, the trace
from inductor to the V
DDQ
output terminal, the
trace from the input ground terminal to the V
DDQ
output ground terminal, the trace from V
DDQ
output to VTTI pin, the trace from VTT pin to
V
TT
output terminal, and the trace from V
TT
output ground terminal to the VTTGND pin.
Power handling and heaksinking of high
current
traces can be improved by also routing the same
high
current traces in the other layers and joined
together with multiple vias.
2. Power components which include the input
capacitor, high
side MOSFET, low
side
MOSFET and V
DDQ
output capacitor of the buck
converter section must be positioned close
together to minimize the current loop. The input
capacitor must be placed close to the drain of the
high
side MOSFET and the source of the
low
side MOSFET.
3. To ensure the proper function of the device,
separated ground connections should be used for
different parts of the application circuit according
to their functions. The input capacitor ground, the
low
side MOSFET source, the V
DDQ
output
capacitor ground, the VCCP decoupling capacitor
ground should be connected to the PGND. The
trace path connecting the source of the low
side
MOSFET and PGND pin should be minimized.
The V
TT
output capacitor ground should be
connected to the VTTGND first with a short
trace, it is then connected to the ground plane of
PGND. The VCCA decoupling capacitor ground,
the ground of the V
DDQ
feedback resistor, the
soft
start capacitor ground, the VTTREF output
capacitor ground should be connected to the
AGND. The AGND pin is then connected directly
through a sense trace to the remote ground sense
point of the PGND, which is usually the ground
of the local bypass capacitor for the load. Never
connect the AGND, PGND and VTTGND
together just under the thermal pad.
4. The thermal pad of the DFN22 package should be
connected to the ground planes in the internal
layer and bottom layer from the copper pad at top
layer underneath the package through six to eight
vias with 0.6 mm hole
diameter to help heat
dissipation and ensure good thermal capability. It
is recommended to use PCB with 1 oz or 2 oz
copper foil. The thermal pad can be connected to
either PGND ground plane or AGND ground
plane but not both.
5. The input capacitor ground terminal, the V
DDQ
output capacitor ground terminal and the source
of the low
side MOSFET must be connected to
the PGND ground plane through multiple vias.
6. Sensitive traces like trace from FBDDQ, trace
from COMP, trace from OCDDQ, trace from
FBVTT and trace from VTTREF should be
avoided from the high
voltage switching nodes
like SWDDQ, BOOST, TGDDQ and BGDDQ.
7. Separate sense trace should be used to connect
the V
DDQ
point of regulation, which is usually
the local bypass capacitor for load, to the
feedback resistor divider to ensure accurate
voltage sensing. The feedback resistor divider
should be place close to the FBDDQ pin.
8. Separate sense trace should be used to connect the
V
TT
point of regulation, which is usually the local
bypass capacitor for load, to the FBVTT pin.
9. Separate sense trace should be used to connect
the V
DDQ
point of regulation to the DDQREF pin
to ensure that the reference voltage to V
TT
is
accurately half of the V
DDQ
voltage.
10. The traces length between the gate driver outputs
and gates of the MOSFETs must be minimized to
avoid parasitic impedance.
11. To ensure normal function of the device, an RC
filter should be placed close to the VCCA pin and
a decoupling capacitor should be placed close to
the VCCP pin.
12. The copper trace area of the switching node which
includes the source of the high
side MOSFET,
drain of the low
side MOSFET and high voltage
side of the inductor should be minimized by using
short wide trace to reduce EMI.
13. A snubber circuit consists of a 3.3 resistor and
1.0 nF capacitor may need to be connected across
the switching node and PGND to reduce the
high
frequency ringing occurring at the rising
edge of the switching waveform to obtain more
accurate inductor current limit sensing of the
V
DDQ
buck converter. However, adding this
snubber circuit will slightly reduce the conversion
efficiency.
14. VTTI should be connected to V
DDQ
output with
wide and short trace if V
DDQ
is used as the
sourcing supply for V
TT
. An input capacitor of at
least 10
F should be added close to the VTTI
pin and bypassed to VTTGND if external voltage
supply is used as the V
TT
sourcing supply.
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NCP5218MNR2G 功能描述:電壓模式 PWM 控制器 2IN1 NOTEBK DDR CNTL RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:1 拓?fù)浣Y(jié)構(gòu):Buck 輸出電壓:34 V 輸出電流: 開關(guān)頻率: 工作電源電壓:4.5 V to 5.5 V 電源電流:600 uA 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝 / 箱體:WSON-8 封裝:Reel
NCP5220 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:3−in−1 PWM Dual Buck and Linear Power Controller
NCP5220AMNR2 功能描述:DC/DC 開關(guān)控制器 3-in-1 PWM Dual Buck RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK
NCP5220AMNR2G 功能描述:DC/DC 開關(guān)控制器 ANA DDR PWER CNTRLR RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK
NCP5220MNR2 功能描述:DC/DC 開關(guān)控制器 3-in-1 PWM Dual Buck RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK
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