參數(shù)資料
型號(hào): NCP5218
廠商: ON SEMICONDUCTOR
英文描述: 2−in−1 Notebook DDR Power Controller
文件頁數(shù): 17/31頁
文件大?。?/td> 463K
代理商: NCP5218
NCP5218
http://onsemi.com
17
Supply Voltage Undervoltage Monitor
The IC continuously monitors VCCA and V
IN
through
VCCA pin and OCDDQ pin respectively. VCCAGD is set
HIGH if VCCA is higher than its preset threshold (derived
from VREF with hysteresis). The IC will enter S5 state if
VCCA fails while in S0 and both VDDQEN and VTTEN
remain HIGH.
Thermal Shutdown
When the chip junction temperature exceeds 150 C, the
entire IC is shutdown. The IC resumes normal operation
only after the junction temperature dropping below 125 C.
Power Good
The PGOOD is an open
drain output of a window
comparator which continuously monitors the VDDQ
output voltage. The PGOOD is pulled low when the VDDQ
rises 12% above or drops 12% below the nominal
regulation point. The PGOOD becomes high impedance
when the VDDQ is within
±
12% of the preset nominal
regulation voltage. A 100 k resistor is recommended to
connect between PGOOD and VCCA as pull
up resistor
for logic level output.
Overvoltage Protection
When the V
DDQ
output is above 106% but below 130%
of the nominal regulation output voltage, the controller
turns off the high
side MOSFET and turns on the low
side
MOSFET to discharge the excessive output voltage. When
the V
DDQ
output voltage goes back down to the nominal
regulation voltage, normal switching cycles are resumed.
When the V
DDQ
output exceeds 130% (typ) of the nominal
regulation voltage for 4 consecutive internal clock cycles,
the controller sets overvoltage fault, the device is latched
off by turning off both the high
side and low
side
MOSFETs. The overvoltage fault latch can be reset and the
controller can be restarted by toggling VDDQEN, VCCA,
or VIN.
Undervoltage Protection
In S3 power
saving mode with reduced switching at
lighter loads, when the V
DDQ
falls below 94% of the
nominal regulation voltage, the reduced switching
frequency is raised up back to the maximum switching
frequency. When V
DDQ
voltage is back to nominal
regulation voltage, the normal S3 power
saving operation
is resumed. In both S0 and S3 modes, when the V
DDQ
falls
below 65% (typ) of the nominal regulation voltage for 4
consecutive internal clock cycles, the undervoltage fault is
set, the device is latched off by turning off both the
high
side and low
side MOSFETs. The output is
discharged by the load current. The load current and output
capacitance determine the discharge rate. Cycling
VDDQEN, VCCA, or V
IN
can reset the undervoltage fault
latch and restart the controller.
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