參數(shù)資料
型號(hào)： NCP5218
廠商： ON SEMICONDUCTOR
英文描述： 2−in−1 Notebook DDR Power Controller
文件頁(yè)數(shù)： 15/31頁(yè)
文件大?。?/td> 463K
代理商： NCP5218
NCP5218
http://onsemi.com
15
DETAILED OPERATING DESCRIPTION
General
The NCP5218
2
in
1 Notebook DDR Power Controller
combines the efficiency of a PWM controller for the V
DDQ
supply, with the simplicity of using a linear regulator for the
V
TT
termination voltage power supply. The V
DDQ
output
can be adjusted through the external potential divider,
while the V
TT
is internally set to track half V
DDQ
.
The inclusion of V
DDQ
power good voltage monitor,
soft
start,
V
DDQ
overcurrent
overvoltage
and
undervoltage
undervoltage monitor, and thermal shutdown makes this
device a total power solution for high current DDR memory
system. The IC is packaged in DFN22.
protection,
protections, supply
V
DDQ
Control Logic
The internal control logic is powered by VCCA. The IC
is enabled whenever V
DDQEN
is high (exceed 1.4 V). An
internal bandgap voltage, V
REF
, is then generated. Once
V
REF
reaches its regulation voltage, an internal signal
V
REFGD
will be asserted. This transition wakes up the
supply undervoltage monitor blocks, which will assert
VCCAGD if VCCA voltage is within certain preset levels.
The control logic accepts external signals at VCCA,
OCDDQ, VDDQEN, VTTEN, and FPWM pins to control
the operating state of the V
DDQ
and V
TT
regulators in
accordance with Table 1. A timing diagram is shown in
Figure 38.
V
DDQ
Switching Regulator in Normal Mode (S0)
The V
DDQ
regulator is a switching synchronous
rectification buck controller directly driving two external
N
Channel power FETs. An external resistor divider sets
the nominal output voltage. The control architecture is
voltage mode fixed frequency PWM with external
compensation and with switching frequency fixed at
400 kHz
15%. As can be observed from Figure 1, the
V
DDQ
output voltage is divided down and fed back to the
inverting input of an internal error amplifier through
FBDDQ pin to close the loop at V
DDQ
= V
FBDDQ
×
(1 + R1/R2). This amplifier compares the feedback voltage
with an internal V
REF
(= 0.800 V) to generate an error
signal for the PWM comparator. This error signal is further
compared with a fixed frequency RAMP waveform
derived from the internal oscillator to generate a
pulse
width
modulated signal. This PWM signal drives
the external N
Channel Power FETs via the TGDDQ and
BGDDQ pins. External inductor L and capacitor C
OUT1
filter the output waveform. The V
DDQ
output voltage
ramps up at a pre
defined soft
start rate when the IC enters
state S0 from S5. When in normal mode, and regulation of
V
DDQ
is detected, signal IN
REGDDQ
will go HIGH to notify
the control logic block.
Input voltage feedforward is implemented to the RAMP
signal generation to reject the effect of wide input voltage
variation. With input voltage feedforward, the amplitude of
the RAMP is proportional to the input voltage.
For enhanced efficiency, an active synchronous switch is
used to eliminate the conduction loss contributed by the
forward voltage of a diode or Schottky diode rectifier.
Adaptive nonoverlap timing control of the complementary
gate drive output signals is provided to reduce large
shoot
through current that degrades efficiency.
Tolerance of V
DDQ
The tolerance of V
FBDDQ
and the ratio of external
resistor divider R1/R2 both impact the precision of V
DDQ
.
With the control loop in regulation, V
DDQ
= V
FBDDQ
×
(1
+ R1/R2). With a worst case (for all valid operating
conditions) V
FBDDQ
tolerance of
range of
2.5% for V
DDQ
= 1.8 V will be assured if the
ratio R1/R2 is specified as 1.2500
1.5%, a worst case
1%.
Table 1. State, Operation, Input and Output Condition Table
Mode
Input Conditions
Operating Conditions
Output Conditions
VCCA
VOCDDQ
VDDQEN
VTTEN
FPWM
VDDQ
VTTREF
VTT
TGDDQ
BGDDQ
PGOOD
S5
Low
X
X
X
X
H
Z
H
Z
H
Z
Low
Low
Low
S5
X
Low
X
X
X
H
Z
H
Z
H
Z
Low
Low
Low
S0
High
High
High
High
X
Normal
Normal
Normal
Normal
Normal
H
Z
S3
High
High
High
Low
High
Standby
Normal
H
Z
Standby
(Power
saving)
Standby
(Power
saving)
H
Z
S3
High
High
High
Low
Low
Normal
Normal
H
Z
Normal
Normal
H
Z
S5
X
X
Low
X
X
H
Z
H
Z
H
Z
Low
Low
Low
V
DDQ
Regulator in Standby Mode (S3)
During state S3, a power
saving mode is activated when
the FPWM pin is pulled to VCCA. In power
saving mode,
the switching frequency is reduced with the V
DDQ
output
current and the low
side FET is turned off after the
detection of negative inductor current, so as to enhance the
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