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NCN6001
http://onsemi.com
5
PIN FUNCTIONS AND DESCRIPTION (continued)
Pin
Description
Type
Name
16
GROUND
SIGNAL
The logic and low level analog signals shall be connected to this ground pin. This pin
must be externally connected to the PWR_GND pin 12. The designer must make sure
no high current transients are shared with the low signal currents flowing into this pin.
17
CRD_CLK
OUTPUT
This pin is connected to the CLK pin of the card connector. The CRD_CLK signal
comes from the clock selector circuit output. An internal active pull down NMOS
device forces this pin to Ground during either the CRD_VCC start up sequence, or
when CRD_VCC = 0 V.
The rise and fall slopes, either FAST or SLOW, of this signal can be programmed by
the MOSI message (Table 2).
Care must be observed, at PCB level, to minimize the pick-up noise coming from the
CRD_CLK line.
18
CRD_DET
INPUT
The signal coming from the external card connector is used to detect the presence of
the card. A built-in pull up low current source biases this pin High, making it active
LOW, assuming one side of the external switch is connected to ground. A built-in
digital filter protect the system against voltage spikes present on this pin.
The polarity of the signal is programmable by the MOSI message, according to the
logic state depicted Table 2. On the other hand, the meaning of the feedback message
contained in the MISO register bit b4, depends upon the SPI mode of operation as
defined here below:
SPI Normal Mode: The MISO bit b4 is High when a card is inserted, whatever be the
polarity of the card detect switch.
SPI Special Mode: The MISO bit b4 copies the logic state of the Card detect switch as
depicted here below, whatever be the polarity of the switch used to handle the
detection:
CRD_DET = Low
→
MISO/b4 = Low
CRD_DET = High
→
MISO/b4 = High
In both cases, the chip must be programmed to control the right logic state (Table 2).
Since the bias current supplied by the chip is very low, typically 5.0 A, care must be
observed to avoid low impedance or cross coupling when this pin is in the Open state.
19
CRD_RST
OUTPUT
This pin is connected to the RESET pin of the card connector. A level translator adapts
the RESET signal from the microcontroller to the external card. The output current is
internally limited to 15 mA.
The CRD_RST is validated when CS = Low and hard wired to Ground when the card
is deactivated, by and internal active pull down circuit.
Care must be observed, at PCB design level, to avoid cross coupling between this
signal and the CRD_CLK clock.
20
CRD_IO
I/O
Pull Up
This pin handles the connection to the serial I/O pin of the card connector. A
bidirectional level translator adapts the serial I/O signal between the card and the
microcontroller. An internal active pull down MOS device forces this pin to Ground
during either the CRD_VCC start up sequence, or when CRD_VCC = 0 V. The
CRD_IO pin current is internally limited to 15 mA.
Care must be observed, at PCB design level, to avoid cross coupling between this
signal and the CRD_CLK clock.