參數(shù)資料
型號(hào): NCN6001DTBR2
廠商: ON SEMICONDUCTOR
元件分類: 其它接口
英文描述: Compact Smart Card Interface IC
中文描述: SPECIALTY INTERFACE CIRCUIT, PDSO20
封裝: LEAD FREE, TSSOP-20
文件頁(yè)數(shù): 27/36頁(yè)
文件大?。?/td> 332K
代理商: NCN6001DTBR2
NCN6001
http://onsemi.com
27
The input clock can be divided by 1/1,
or
, depending
upon the specific application, prior to be applied to the smart
card driver. On the other hand, the positive and negative
going slopes of the output clock (CRD_CLK) can be
programmed to optimize the operation of the chip
(Table 10). The slope of the output clock can be
programmed on the fly, independently of either the
CRD_VCC voltage or the operating frequency, but care
must be observed as the CRD_RST will reflect the logic
state present at MOSI/b4 register.
Table 10. Output Clock Rise and Fall Time Selection
B0
B1
CRD_CLK
Division Ratio
CRD_CLK
SLO_SLP
CRD_CLK
FST_SLP
0
0
-
Output Clock = Low
Output Clock = Low
0
1
1
10 ns (typ.)
2 ns (typ.)
1
0
1/2
10 ns (typ.)
2 ns (typ.)
1
1
1/4
10 ns (typ.)
2 ns (typ.)
Figure 26. Force CRD_CLK to Low
Figure 27. Force CRD_CLK to Active Mode
Figure 28. CRD_CLK Programming
Note: Waveforms recorded without external compensation
network.
Figure 29. CRD_CLK Operating Low Speed (Top Trace),
Full Speed (Bottom Trace)
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