參數(shù)資料
型號: NCN6001DTBR2
廠商: ON SEMICONDUCTOR
元件分類: 其它接口
英文描述: Compact Smart Card Interface IC
中文描述: SPECIALTY INTERFACE CIRCUIT, PDSO20
封裝: LEAD FREE, TSSOP-20
文件頁數(shù): 17/36頁
文件大?。?/td> 332K
代理商: NCN6001DTBR2
NCN6001
http://onsemi.com
17
DATA I/O LEVEL SHIFTER
The level shifter accommodates the voltage difference
that might exist between the microcontroller and the smart
card. A pulsed accelerator built-in circuit provides the fast
positive going transient according to the ISO7816-3
specifications. The basic I/O level shifter is depicted in
Figure 7.
LOGIC AND
LEVEL SHIFT
Q4
Q3
Q2
R2
18 k
Q5
GND
CRD_VCC
13
CRD_IO
20
CRD_VCC
CARD ENABLE
POR
SEQ 1
200 ns
200 ns
Q1
R1
18 k
EN_RPU
6
I/O
1
V
CC
9
V
CC
P
U1
VCC
Q5
GND
SYNC
MOSI/b3
MOSI/b2
From MOSI
decoding
Figure 7. Basic I/O Internal Circuit
The transaction is valid when the Chip Select pin is Low,
the I/O signal being Open Drain or Totem Pole on either
sides.
Since the device can operate either in a single or a multiple
card system, provisions have been made to avoid CRD_IO
current overload. Depending upon the selected mode of
operation (ASYNC. or Sync), the card I/O line is
respectively connected to either I/O pin 1, or to the MOSI
register byte bit 2. On the other hand, the logic level present
at the card I/O is feedback to the C via the MISO register
bit 3. The logic level present at pin 6 controls the connection
of the internal pull up as depicted in Table 6.
Table 6. I/O Pull Up Resistor True Table
EN_RPU
I/O Pull Up Resistor
Device
Operation
Low
Open, 18 k disconnected
Parallel Mode
High
Internal 18 k pull up active
Single Device
NOTE:
18 k typical value
Figure 8. Typical I/O Rise and Fall Time
NOTE: Both sides of the interface run with open drain load
(worst case condition).
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