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參數(shù)資料
| 型號： | NB3F8L3010CMNR4G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 3/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FANOUT BUFFER 3:10 32QFN |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 扇出緩沖器（分配），多路復(fù)用器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:10 |
| 差分 - 輸入:輸出： | 是/無 |
| 輸入： | HCSL, LVDS, LVPECL, SSTL, 晶體 |
| 輸出： | LVCMOS，LVTTL |
| 頻率 - 最大： | 200MHz |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-QFN（5x5） |
| 包裝： | 帶卷 (TR) |
NB3F8L3010C
http://onsemi.com
11
Differential Clock Input Interface
The CLK / CLK accept LVDS, LVPECL, SSTL, HCSL
differential signals. Signals must meet the VPP and VCMR
examples for the CLK / CLK input with builtin 50
W
terminations driven by the most common driver types. The
input interfaces suggested here are examples only. If the
driver is from another vendor, use their termination
recommendation. Please consult with the vendor of the
driver component to confirm the driver termination
requirements.
Figure 9. CLK / CLK Input Driven by 3.3 V LVPECL
Driver (Thevenin Parallel Termination)
Figure 10. CLK / CLK Input Driven by 3.3 V
LVPECL Driver (“Y” Parallel Termination)
Figure 11. CLK / CLK Input Driven by a 3.3 V
HCSL Driver
Figure 12. CLK / CLK Input Driven by 3.3 V
LVDS Driver
Figure 13. CLK / CLK Input Driven by 2.5 V SSTL Driver
Zo = 50 W
LVPECL
84 W
GND = 0.0 V
84 W
Zo = 50 W
Differential
In
Qx
CLKx
Zo = 50 W
LVPECL
50 W
GND = 0.0 V
50 W
Zo = 50 W
Differential
In
Qx
CLKx
VDD = +3.3 V
125 W
GND = 0.0 V
VDD = +3.3 V
GND = 0.0 V
VDD = +3.3 V
50 W
GND = 0.0 V
VDD = +3.3 V
GND = 0.0 V
VDD = +3.3 V
Zo = 50 W
HCSL
50 W
GND = 0.0 V
50 W
Zo = 50 W
Differential
In
Qx
CLKx
GND = 0.0 V
VDD = +3.3 V
GND = 0.0 V
VDD = +3.3 V
33 W (Opt)
Zo = 50 W
SSTL
120 W
GND = 0.0 V
120 W
Zo = 50 W
Differential
In
Qx
CLKx
VDD = +2.5 V
120 W
GND = 0.0 V
VDD = +3.3 V
GND = 0.0 V
VDD = +2.5 V
Zo = 50 W
LVDS
100 W
Zo = 50 W
Differential
In
Qx
CLKx
GND = 0.0 V
VDD = +3.3 V
GND = 0.0 V
VDD = +3.3 V
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