參數(shù)資料
型號: NB3F8L3010CMNR4G
廠商: ON Semiconductor
文件頁數(shù): 1/13頁
文件大?。?/td> 0K
描述: IC FANOUT BUFFER 3:10 32QFN
標準包裝: 1,000
類型: 扇出緩沖器(分配),多路復用器
電路數(shù): 1
比率 - 輸入:輸出: 3:10
差分 - 輸入:輸出: 是/無
輸入: HCSL, LVDS, LVPECL, SSTL, 晶體
輸出: LVCMOS,LVTTL
頻率 - 最大: 200MHz
電源電壓: 2.375 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-QFN(5x5)
包裝: 帶卷 (TR)
Semiconductor Components Industries, LLC, 2014
February, 2014 Rev. 4
1
Publication Order Number:
NB3F8L3010C/D
NB3F8L3010C
3.3V / 2.5V / 1.8V / 1.5V 1:10
LVCMOS Fanout Buffer
Description
The NB3F8L3010C is a 3:1:10 Clock / Data fanout buffer operating
on a 3.3 V / 2.5 V Core VDD and two flexible 3.3 V / 2.5 V / 1.8 V /
1.5 V VDDOn supplies which must be equal or less than VDD.
A Mux selects between a Crystal input, or either of two
differential/SE Clock / Data inputs. Differential Inputs accept
LVPECL, LVDS, HCSL, or SSTL and SingleEnded levels. The
MUX control lines, SEL0 and SEL1, select CLK0/CLK0,
CLK1/CLK1, or Crystal input pins per Table 3. The Crystal input is
disabled when a Clock input is selected. Output enable pin, OE,
synchronously forces a High Impedance state (HZ) when Low per
Table 4.
Outputs consist of 10 singleended LVCMOS outputs.
Features
Ten CMOS / LVTTL Outputs up to 200 MHz
Differential Inputs Accept LVPECL, LVDS, HCSL, or SSTL
Crystal Oscillator Interface
Crystal Input Frequency Range: 10 MHz to 50 MHz
Output Skew: 10 ps Typical
Additive RMS Phase Jitter @ 125 MHz, (12 kHz – 20 MHz): 0.03 ps
(Typical)
Synchronous Output Enable
Output Defined Level When Input is Floating
Power Supply Modes:
Single 3.3 V
Single 2.5 V
Mixed 3.3 V
± 5% Core/2.5 V ± 5% Output Operating Supply
Mixed 3.3 V
± 5% Core/1.8 V ± 0.2 V Output Operating Supply
Mixed 3.3 V
± 5% Core/1.5 V ± 0.15 V Output Operating Supply
Mixed 2.5 V
± 5% Core/ 1.8 V ± 0.2 V Output Operating Supply
Mixed 2.5 V
± 5% Core /1.5 V ± 0.15 V Output Operating Supply
Two Separate Output Bank Power Supplies
Industrial temp. range -40°C to 85°C
These are PbFree Devices
Applications
Clock Distribution
Networking and Communications
High End Computing
Wireless and Wired Infrastructure
End Products
Servers
Ethernet Switch/Routers
ATE
Test and Measurement
MARKING
DIAGRAM
QFN32
G SUFFIX
CASE 488AM
http://onsemi.com
See detailed ordering and shipping information page 12 of this
data sheet.
ORDERING INFORMATION
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= PbFree Package
32
1
NB3F8L
3010C
AWLYYWWG
1
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