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參數(shù)資料
| 型號： | NB3F8L3010CMNR4G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 13/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FANOUT BUFFER 3:10 32QFN |
| 標(biāo)準包裝： | 1,000 |
| 類型： | 扇出緩沖器（分配），多路復(fù)用器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:10 |
| 差分 - 輸入:輸出： | 是/無 |
| 輸入： | HCSL, LVDS, LVPECL, SSTL, 晶體 |
| 輸出： | LVCMOS，LVTTL |
| 頻率 - 最大： | 200MHz |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-QFN（5x5） |
| 包裝： | 帶卷 (TR) |
NB3F8L3010C
http://onsemi.com
9
Differential Input with SingleEnded Interconnect
Refer to Figure 5 to interconnect a singleended to a
Differential Pair of inputs. The reference bias voltage VREF
= VDD/2 is generated by the resistor divider of R3 and R4.
Bypass capacitor (C1) can filter noise on the DC bias. This
bias circuit should be located as close to the input pin as
possible. Adjust R1 and R2 to common mode voltage of the
signal input swing to preserve duty cycle.
This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs)
equals the transmission line impedance. In addition,
matched termination by R1 and R2 will attenuate the signal
amplitude in half. Termination may be done by using Rs or
by using R1 and R2. First, Rs = 0 and then R3 and R4 in
parallel should equal the transmission line impedance. For
most 50
W applications, R1 and R2 can be 100 W. The
differential input can handle full rail LVCMOS signaling,
but it is recommended that the amplitude be reduced. The
datasheet specifies a differential amplitude which needs to
be doubled for a single ended equivalent stimulus. VILmin
cannot be less than 0.3 V and VIHmax cannot be more than
VDD + 0.3 V. The datasheet specifications are characterized
and guaranteed by using a differential signal.
Zo = 50 W
Single
C1
0.1 mF
R2
100 W
Z0 = RO + Rs
GND = 0.0
VDD
R1
100 W
Rs
RO
Ended
Driver
GND = 0.0
VDD
GND = 0.0
R4
1 kW
R3
1 kW
Differential In
VDD
CLKx
Figure 5. Differential Input with Singleended Interconnect
Crystal Input Interface
The device has been characterized with 18 pF parallel
resonant crystals. The capacitor values, C1 and C2, shown
in Figure 6 below as 15 pF were determined using an 18 pF
parallel resonant crystal and were chosen to minimize the
ppm error. The optimum C1 and C2 values can be slightly
adjusted for different board layouts.
Figure 6. Crystal Input Interface
CLOCK Overdriving the XTAL Interface
The XTAL_IN input can accept a singleended LVCMOS
signal through an AC coupling capacitor. A general
LVCMOS interface diagram is shown in Figure 7 and a
general LVPECL interface in Figure 8. The XTAL_OUT
pin must be left floating. The maximum amplitude of the
input signal should not exceed 2 V and the input edge rate
can be as slow as 10 ns. This configuration requires that the
output impedance of the driver (Ro) plus the series
resistance (Rs) equals the transmission line impedance. In
addition, matched termination at the crystal input will
attenuate the signal in half. This can be done in one of two
ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50
W applications,
R1 and R2 can be 100
W. This can also be accomplished by
removing R1 and making R2 50
W. By overdriving the
crystal oscillator, the device will be functional, but note, the
device performance is guaranteed by using a quartz crystal.
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