參數(shù)資料
型號: NB3F8L3010CMNR4G
廠商: ON Semiconductor
文件頁數(shù): 12/13頁
文件大?。?/td> 0K
描述: IC FANOUT BUFFER 3:10 32QFN
標(biāo)準(zhǔn)包裝: 1,000
類型: 扇出緩沖器(分配),多路復(fù)用器
電路數(shù): 1
比率 - 輸入:輸出: 3:10
差分 - 輸入:輸出: 是/無
輸入: HCSL, LVDS, LVPECL, SSTL, 晶體
輸出: LVCMOS,LVTTL
頻率 - 最大: 200MHz
電源電壓: 2.375 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-QFN(5x5)
包裝: 帶卷 (TR)
NB3F8L3010C
http://onsemi.com
8
PARAMETER MEASUREMENT INFORMATION
Differential Input Level
Within Device Output Skew
Output Enable /Disable
(OE HIGH = Enabled)
Output Duty Cycle / Pulse Width / Period
Output Rise/Fall Time
MUX Isolation
Xpoint
VCMR
VPP
VDD
CLK
GND
VDDOn/2
tsk(0)
Qx
Qv
VDD/2
tDIS
VDDOn/2
tEN
VDD
VOH
VOL
VDDOn/2
0 V
OE
Qx
VDDOn/2
tPW
tPeriod
Qx
odc = (tPW / tPeriod) x 100%
Qx
tR
tF
80%
Spectrum of Output Signal Qx
MUX selects
active inpu t clock
signal
MUX
= A0 - A1
MUX selects
static input
fc
(Fundamental)
Amplitud
e(dB)
Frequ ency (Hz)
A0
A1
_ISOL
Figure 4. Operational Waveforms and MUX Input Isolation Plot
20%
APPLICATION INFORMATION
Recommendations for Unused LVCMOS Output Pins
Inputs:
CLK/CLK Inputs
For applications not requiring the use of the differential
input, both CLK and CLK can be left floating. Though not
required, but for additional protection, a 1 k
W resistor can be
tied from CLK to ground.
Crystal Inputs
For applications not requiring the use of the crystal
oscillator input, both XTAL_IN and XTAL_OUT can be left
floating. Though not required, but for additional protection,
a 1 k
W resistor can be tied from XTAL_IN to ground.
LVCMOS Outputs
A 33
W series terminating resistor may be used on each
clock output if the trace is longer than 1 inch.
LVCMOS Control Pins
All control pins have internal pulldowns; additional
resistance is not required but can be added for additional
protection. A 1 k
W resistor can be used.
Power Supplies
VDD is the power supply for the core and input circuitry.
VDDOA and VDDOB are two separate positive power
supplies for two banks of outputs:
VDDOA pins 2 and 6 are connected internally for outputs
Q0 Q4.
VDDOB pins 19 and 23 are connected internally for outputs
Q5 Q9.
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