參數(shù)資料
型號： NAND04GW3C2AN6E
廠商： 意法半導(dǎo)體
英文描述： 4Gbit, 2112 Byte Page, 3V, Multi-level NAND Flash Memory
中文描述： 4Gbit的，2112字節(jié)的頁，3V供電，多級NAND閃存
文件頁數(shù)： 21/51頁
文件大?。?/td> 374K
代理商： NAND04GW3C2AN6E
NAND04GA3C2A, NAND04GW3C2A
6 Device operations
21/51
The Ready/Busy signal can be used to monitor the start of the operation. During the latency
period the Ready/Busy signal goes Low, after this the Ready/Busy signal goes High, even if
the device is internally downloading page n+1.
Once the Cache Read operation has started, the Status Register can be read using the
Read Status Register command.
During the operation, SR5 can be read, to find out whether the internal reading is ongoing
(SR5 = ‘0’), or has completed (SR5 = ‘1’), while SR6 indicates whether the Cache Register
is ready to download new data.
To exit the Cache Read operation an Exit Cache Read command must be issued (see
Table 8
).
Figure 7.
Cache Read Operation
6.5
Page Program
The Page Program operation is the standard operation to program data to the memory
array. Generally, data is programmed sequentially, however the device does support
Random Input within a page.
The memory array is programmed by page, however partial page programming is allowed
where any number of Bytes (1 to 2112) can be programmed.
Only one consecutive partial page program operations is allowed on the same page. After
exceeding this a Block Erase command must be issued before any further program
operations can take place in that page.
I/O
RB
Inputs
ai08661
00h
Read
Setup
Code
31h
Cache
Read
Confirm
Code
Busy
(Read Busy time)
1st page
Data Output
2nd page
3rd page
last page
34h
Exit
Cache
Read
Code
Block N
相關(guān)PDF資料
PDF描述
NAND128R3A2AZA1 128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
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NAND128R4A2BZA1E 128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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