參數(shù)資料
型號： MX98715AL
英文描述： SINGLE CHIP FAST ETHERNET NIC CONTROLLER
中文描述： 單晶片快速以太網(wǎng)卡控制器
文件頁數(shù)： 9/32頁
文件大?。?/td> 215K
代理商： MX98715AL
9
P/N:PM0537
REV. 1.2, FEB. 24, 1999
MX98715A
5.1.8 PCI BASE EXPANSION ROM ADDRESS REGISTER ( PBER ) ( Offset 33h-30h )
bit 0 : Address Decode Enable, decoding will be enabled if only both enable bit in PFCS<1> and this expansion ROM
register are 1.
bit 10 - 1 : not use
bit 31 - 11 : Defines the upper 21 bits of expansion ROM base address.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Expansion ROM Base Address (upper 21 bit)
Address Decode Enable
0 0 0 0 0 0 0
5.1.10 INTERRUPT REGISTER ( PFIT ) ( Offset 3Fh-3Ch )
bit 7 - 0 : Interrupt Line, system BIOS will writes the routing information into this field, driver can use this information
to determine priority and interrupt vector.
bit 15 - 8 : Interrupt Pin, fixed to 01h which use INTA#.
bit 31 - 24 : Max_Lat which is a maximum period for a access to PCI bus.
bit 23 - 16 : Min_Gnt which is the maximum period that MX98715A needs to finish a brust PCI cycle.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Min-Gnt
Interrupt Pin
Interrupt Line
Max_Lat
0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0
5.1.9 PCI CAPABILITY POINTER REGISTER ( PFCP ) ( Offset 37h-34h )
bit 7- 0 : Capability pointer (Cap_Ptr) is set to 44h if PMEB is connected to PCI bus, otherwise 00.
bit 31- 8 : reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Capability Pointer (Set to 44h)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MX98715BEC 制造商:MCNIX 制造商全稱:Macronix International 功能描述:APPLICATION NOTE
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MX98726AEC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Controller Miscellaneous - Datasheet Reference
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