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參數(shù)資料
| 型號： | MX98715AL |
| 英文描述： | SINGLE CHIP FAST ETHERNET NIC CONTROLLER |
| 中文描述： | 單晶片快速以太網(wǎng)卡控制器 |
| 文件頁數(shù)： | 1/32頁 |
| 文件大小： | 215K |
| 代理商： | MX98715AL |
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1. FEATURES
A single chip solution integrates 100/10 Base-T fast
Ethernet MAC, PHY and PMD
Fully comply to IEEE 802.3u specification
Operates over 100 meters of STP and category 5
UTP cable
Fully comply to PCI spec. 2.1 up to 33MHz
Fully comply to Advanced Configuration and Power
Interface (ACPI) Rev 1.0
Fully comply to PCI Bus Power Management Inter-
face spec. Rev 1.0
Support full and half duplex operations in both 100
Base-TX and 10 Base-T mode
Magic Packet
TM
mode to support Remote-Wake-Up
and Remote-Power-On
100/10 Base-T NWAY auto negotiation function
Large on-chip FIFOs for both transmit and receive
operations without external local memory
Bus master architecture with linked host buffers deliv-
ers the most optimized performance
32-bit bus master DMA channel provides ultra low
CPU utilization, best fit in server and windows appli-
cation.
Proprietary Adaptive Network Throughput Control
(ANTC) technology to optimize data integrity and
throughput
Support up to 64K bytes boot ROM interface
Three levels of loopback diagnositic capability
Support a variety of flexible address filtering modes
with 16 CAM address and 512 bits hash
MicroWire interface to EEPROM for customer's IDs
and configuration data
Single +5V power supply, CMOS technology, 128-pin
PQFP package/LQPF package
( Magic Packet Technology is a trademark of Advanced
Micro Device Corp. )
2. GENERAL DESCRIPTIONS
The MX98715A controller is an IEEE802.3u compliant
single chip 32-bit full duplex, 10/100Mbps highly inte-
grated Fast Ethernet combo solution, designed to ad-
dress high performance local area networking (LAN)
system application requirements.
MX98715A's PCI bus master architecture delivers the
optimized performance for future high speed and pow-
erful processor technologies. In other words, the
MX98715A not only keeps CPU utilization low while
maximizing data throughput, but it also optimizes the
PCI bandwidth providing the highest PCI bandwidth uti-
lization. To further reduce maintenance costs the
MX98715A uses drivers that are backward compatible
with the original MXIC MX98713 series controllers.
The MX98715A contains a PCI local bus glueless inter-
face, a Direct Memory Access (DMA) buffer manage-
ment unit, an IEEE802.3u-compliant Media Access Con-
troller (MAC), large Transmit and Receive FIFOs, and
an on-chip 10 Base-T and 100 Base-TX transceiver sim-
plifying system design and improving high speed signal
quality. Full-duplex operation are supported in both 10
Base-T and 100 Base-TX modes that increases the
controller's operating bandwidth up to 200Mbps.
Equipped with intelligent IEEE802.3u-compliant auto-
negotiation, the MX98715A-based adapter allows a
single RJ-45 connector to link with the other IEEE802.3u-
compliant device without re-configuration.
In MX98715A, an innovative and proprietary design
"Adaptive Network Throughput Control" (ANTC) is built-
in to configure itself automatically by MXIC's driver based
on the PCI burst throughput of different PCs. With this
proprietary design, MX98715A can always optimize its
operating bandwidth, network data integrity and through-
put for different PCs.
The MX98715A features Remote-Power-On and Re-
mote-Wake-Up capability and is compliant with the Ad-
vanced Configuration and Power Interface version 1.0
(ACPI). This support enables a wide range of wake-up
capabilities, including the ability to customize the con-
tent of specified packet which PC should be responded
to, even when it is in a low-power state. PCs and work-
stations could take advantage of these capabilities of
being waked up and served simultaneously over the net-
work by remote server or workstation. It helps organi-
zations reduce their maintenance cost of PC network.
The 32-bit multiplexed bus interface unit of MX98715A
provides a direct interface to a PCI local bus, simplifing
the design of an Ethernet adapter in a PC system. With
its on-chip support for both little and big endian byte
alignment, MX98715A can also address non-PC appli-
cations.
1
P/N:PM0537
REV. 1.2, FEB. 24, 1999
MX98715A
SINGLE CHIP FAST ETHERNET NIC CONTROLLER
PRELIMINARY
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MX98727 | SINGLE CHIP PCI/CARDBUS FAST ETHERNET CONTROLLER |
| MX98742 | FEBC 100 Base Fast Ethernet Bridge Controller |
| MX98902A(PLCC) | LAN Node Controller |
| MX98902A(PQFP) | LAN Node Controller |
| MX98902A(SQFP) | LAN Node Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MX98715BEC | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:APPLICATION NOTE |
| MX98725 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE CHIP FAST ETHERNET NIC CONTROLLER |
| MX98726 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER WITH uP INTERFACE |
| MX98726AEC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Controller Miscellaneous - Datasheet Reference |
| MX98726EC | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER WITH uP INTERFACE |
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