參數(shù)資料
型號(hào)： MX98715AL
英文描述： SINGLE CHIP FAST ETHERNET NIC CONTROLLER
中文描述： 單晶片快速以太網(wǎng)卡控制器
文件頁(yè)數(shù)： 26/32頁(yè)
文件大小： 215K
代理商： MX98715AL
26
P/N:PM0537
REV. 1.2, FEB. 24, 1999
MX98715A
5.2.15 Magic Packet Register (CSR16)
Field
bit 31:23
bit 15:0
bit 22
Name
reserved
reserved
MPE
Description
Magic Packet Enable, set to enable Magic Packet Mode
Sleep mode and MPE mode can be used seperately. When Sleep and MPE are both set, the Sleep mode dominate
MPE, i.e. no magic packet can be detected since both TX and RX channel are shut off in sleep mode. On the
detection of magic packet, the MPI interrupt bit at CSR5<28> can be set to generate a PCI interrupt if CSR7<28>
MPIE is set.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MPE (Magic Packet Enable)
5.2.16 Nway Status Register (CSR20)
Field
31
30
29
28
27
16
Name
T4
100TXF
100TXH
10TXF
10TXH
PCITEST
Description
T4 mode is accepted, read only
100Base-TX full duplex is accepted, read only
100Base-TX half duplex is accepted, read only
10Base-T duplex is accepted, read only
10Base-T half duplex is accepted, read only
Default is 0 after Power-on reset. Reserved for PCI bus test purpose, must be set
1 by software for normal operation.
Default is 0 after Power-on reset. Reserved for tranceiver equalization test pur-
pose, must be set 1 by software for normal operation.
12
EQTEST
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCITEST
EQTEST
100T4
100TXF
100TXH
10TXF
10TXH
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