參數(shù)資料
型號： MX98715AL
英文描述： SINGLE CHIP FAST ETHERNET NIC CONTROLLER
中文描述： 單晶片快速以太網(wǎng)卡控制器
文件頁數(shù)： 7/32頁
文件大小： 215K
代理商： MX98715AL
7
P/N:PM0537
REV. 1.2, FEB. 24, 1999
MX98715A
5.1.3 PCI REVISION REGISTER ( PFRV ) ( Offset 0Bh-08h )
bit 3 - 0 : Step Number, range from 0 to Fh.
bit 7 - 4 : Revision Number, fixed to 2h for MX98715A
bit 15 - 8 : not used
bit 23 - 16 : Subclass, fixed to 0h.
bit 31 - 24 : Base Class, fixed to 2h.
5.1.4 PCI LATENCY TIMER REGISTER ( PFLT ) (Offset 0Fh-0Ch)
bit 0 - bit 7 : System cache line size in units of 32 bit word, device driver should use this value to program CSR0<15:14>.
bit 8 - bit 15 : Configuration Latency Timer, when MX98715A assert FRAME#, it enables its latency timer to count.
If MX98715A deasserts FRAME# prior to timer expiration, then timer is ignored. Otherwise, after timer expires,
MX98715A initiates transaction termination as soon as its GNT# is deasserted.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Base Class
Subclass
Step Number
Revision Number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Configuration Latency Timer
System cache line size
PFLT Register (0Fh-0Ch)
bit 24:Data parity Report, is set to 1 only if PERR# active and PFCS<6> is also set.
bit 26-25:Device Select Timing of DEVSELB pin.
bit 27:not used
bit 28:Receive Target Abort, is set to indicate a transaction is terminated by a target abort.
bit 29:Receive Master Abort, is set to indicate a master transaction with Master abort.
bit 30:Signal System Error, is set to indicate assertion of SERR#.
bit 31:Detected Parity Error, is set whenever a parity error detected regardless of PFCS<6>.
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