參數(shù)資料
型號(hào): MX98206EC
廠商: MACRONIX INTERNATIONAL CO LTD
元件分類: 微控制器/微處理器
英文描述: 8-Port Dual-Speed Ethernet Switch Controller(8端口、雙速以太網(wǎng)開關(guān)控制器)
中文描述: 8 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP208
封裝: PLASTIC, QFP-208
文件頁(yè)數(shù): 1/37頁(yè)
文件大?。?/td> 549K
代理商: MX98206EC
1
P/N:PM0661
REV. 0.2, JUN. 09, 2000
MX98206EC
8-Port Dual-Speed Ethernet Switch Controller
FEATURES
Single-chip 8-port 10/100Mbps wire-speed switched
Ethernet controller.
Integration of 8 dual-speed, full/half duplex capable
Media Access Controllers (MACs) with RMII interfaces.
Support Store-and-Forward switching scheme.
Support 2.1Gbps (@66MHz) expansion (inter-switch)
bus interface.
Support source/destination MAC address lookup, learn-
ing, and aging within built-in storage of 1K MAC ad-
dress.
Optional MII port in replacement of the cascading in-
terface.
GENERAL DESCRIPTION
The MX98206EC is a 8-port 10/100Mbps single-chip
shared-memory Ethernet switch controller. A desktop or
departmental switched Ethernet solution can be achieved
by combining MX98206EC, the necessary physical de-
vices and low-cost memory. All 8 ports are full-duplex
capable to provide private 20/200Mbps bandwidth con-
nection to power users or servers through external physi-
cal (PHY) layers. System manufacturers can cascade 2
MX98206EC switch controllers to build a 16-port 10/
100Mbps switched Ethernet box easily.
MX98206EC supports store-and-forward switching
scheme with built-in storage of 1K MAC addresses. The
function modules integrated in controller include 8 full-
duplex compatible media access controller with RMII
interface to PHYs, address resolution logic (ARL) for MAC
address learning and recognition, queue manager, and
expansion bus interface for 2 MX98206ECs cascading.
It fully complies with IEEE Std. 802.3/802.3u specifica-
tion, and supports MDC/MDIO interface for physical layer
management with industrial standard physical devices.
The flow control mechanism is provided to prevent buffer
overflow that would force controller to lose packets. Con-
troller will monitor the traffic through receive terminal of
each physical port, and frame queuing status on the data
buffer. Some watermarks are set. As soon as data buffer
PRELIMINARY
Support IEEE802.3x compliant flow control for FDX
and back-pressure flow control for HDX.
Support up to 2MB SSRAM (pipeline type, or flow
through type) as data buffer.
Serial EEPROM interface for auto-configuration.
Broadcast storm control.
LED interface for utilization indication of each port.
Cascade 2 switch controllers to construct 16 10/
100MBps switched Ethernet ports in a box easily with-
out extra logic.
3.3V COMS technology, package in 208-pin PQFP.
is over the warning threshold, flow control mechanism is
triggered to deter the underlying host(s) to transmit frames
for some time. For half-duplex operation port(s), jam pat-
tern is issued to the attached host. For full-duplex opera-
tion port(s), specific "pause" frame of IEEE Std. 802.3x
is issued to host. Moreover, user can program the thresh-
old of broadcast frame storage to discard over-loaded
ones to prevent potential of broadcast storming from
occurring. After buffer fullness drops in the safe margin,
controller releases flow control state to allow physical
ports to work in normal condition.
Per port utilization information can be retrieved through
serial LED interface. User can program the control regis-
ter for "all-port" display mode or "select-port" display mode
with 8-bit indication or 5-bit indication.
System manufactures’ design flexibility is our concern
too. MX98206EC provides expansion bus interface for 2
MX98206ECs cascading. Simple bus protocol is utilized
to control traffic transaction on expansion bus.
MX98206EC also provides an optional MII port for gen-
eral connection in case no expansion bus is used. In 16-
port Fast Ethernet switch paradigm, only one EEPROM
is required for auto-configuration. Figure 1 and Figure 2
illustrate the functional block diagrams of MX98206EC,
and Figure 3 depicts the pin assignment of MX98206EC.
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