參數(shù)資料
型號: MX98705
廠商: MACRONIX INTERNATIONAL CO LTD
元件分類: 網(wǎng)絡(luò)接口
英文描述: 100 Base-TX PHY-PMD Transceiver(100 Base-TX PHY-PMD 收發(fā)器)
中文描述: DATACOM, ETHERNET TRANSCEIVER, PQFP52
封裝: PLASTIC, QFP-52
文件頁數(shù): 1/10頁
文件大?。?/td> 56K
代理商: MX98705
1
P/N:PM0471
REV. 1.4, JUN. 30, 1998
1. FEATURES
Complies with IEEE 802.3 Standards
Integral 10 Mb/s Buffer for Dual 10 Mb/s&100 Mb/s
Applications
Baseline Wander correction
Adapative Equalization
25 MHz to 125 MHz Transmit Clock Multiplier
Five Bit TTL Nibble at 25 MHz Input/Output
25 MHz received recovery clock
Operates over 100 Meters of STP and Category 5 UTP
Cable (>7.5 dB)
Single +5V Supply
52 PQFP package
2. GENERAL DISCRIPTION
The MX98705 is a fully intergrated physical layer device
supporting 100Base-TX or FDDI over copper applications.
The MX98705 integrates 125 MHz clock recovery/gen-
eration, receive adaptive equalization, and baseline wan-
der correction, it provides 5-bit parallel interface to any
MAC controller.
3. BLOCK DIAGRAM
The MX98705 receive section includes an adaptive equal-
izer with DC baseline wander compensation, MLT-3 to
NRZ decoder, and a 125 MHz receive clock recovery
circuit. The transmit section provide NRZ to MLT-3 for
100Base-TX and a buffer for 10 Mb/s application.
MX98705
100 BASE-TX PHY-PMD TRANSCEIVER
PRELIMINARY
TXPLL
Clock recovery
SDO
10TIP/N
PXIP/N
N10/100
ILBEN
TXOP/N
10M
EQ
100M
TDAT0-4
Signal detect
EQ
Baseline wander
Voltage
RXPLL
NRZI to MLT3
RDA0-4
DRIVER
4. PIN CONFIGURATION
39
38
37
36
35
34
33
32
31
30
29
28
27
1
2
3
4
5
6
7
8
9
10
11
12
13
GND
NC
NC
RSCLK
SDO
VDD
NC
NC
GND
NC
NC
VDD
VDD
GND
NC
NC
N10/100
LBEN
VDD
TXOE
VDD
RFA
RFB
GND
GND
GND
MX98705
4
4
4
4
4
4
4
4
4
4
5
5
5
2
2
2
2
2
2
2
1
1
1
1
1
1
T
T
T
T
T
C
V
T
R
R
R
R
R
V
R
G
T
T
V
1
1
E
V
R
R
G
相關(guān)PDF資料
PDF描述
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