參數(shù)資料
型號(hào)： MX98206
廠商： MACRONIX INTERNATIONAL CO LTD
元件分類： 微控制器/微處理器
英文描述： 8-Port Dual-Speed Ethernet Switch Controller(8端口、雙速以太網(wǎng)開(kāi)關(guān)控制器)
中文描述： 8 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP208
封裝： PLASTIC, QFP-208
文件頁(yè)數(shù)： 1/33頁(yè)
文件大?。?/td> 506K
代理商： MX98206
1
P/N:PM0661
REV. 0.1, FEB. 10, 2000
MX98206
8-Port Dual-Speed Ethernet Switch Controller
FEATURES
Single-chip 8-port 10/100Mbps wire-speed switched
Ethernet controller.
Integration of 8 dual-speed, full/half duplex capable
Media Access Controllers (MACs) with RMII interfaces.
Support Store-and-Forward switching scheme.
Support 2.1Gbps (@66MHz) expansion (inter-switch)
bus interface.
Support source/destination MAC address lookup, learn-
ing, and aging within built-in storage of 1K MAC ad-
dress.
GENERAL DESCRIPTION
The MX98206 is a 8-port 10/100Mbps single-chip shared-
memory Ethernet switch controller. A desktop or depart-
mental switched Ethernet solution can be achieved by
combining MX98206, the necessary physical devices and
low-cost memory. All 8 ports are full-duplex capable to
provide private 20/200Mbps bandwidth connection to
power users or servers through external physical (PHY)
layers. System manufacturers can cascade 2 MX98206
switch controllers to build a 16-port 10/100Mbps switched
Ethernet box easily.
MX98206 supports store-and-forward switching scheme
with built-in storage of 1K MAC addresses. The function
modules integrated in controller include 8 full-duplex com-
patible media access controller with RMII interface to
PHYs, address resolution logic (ARL) for MAC address
learning and recognition, queue manager, and expansion
bus interface for 2 MX98206s cascading. It complies fully
with IEEE Std. 802.3/802.3u specification, and supports
MDC/MDIO interface for physical layer management with
industrial standard physical devices.
The flow control mechanism is provided to prevent buffer
overflow that would force controller to lose packets. Con-
troller will monitor the traffic through receive terminal of
PRELIMINARY
Support IEEE802.3x compliant flow control for FDX
and back-pressure flow control for HDX.
Support up to 2MB SSRAM (pipeline type, or flow
through type) as data buffer.
Serial EEPROM interface for auto-configuration.
Broadcast storm control.
LED interface for utilization indication of each port.
Cascade 2 switch controllers to construct 16 10/
100MBps switched Ethernet ports in a box easily with-
out extra logic.
3.3V COMS technology, package in 208-pin PQFP.
each physical port, and frame queuing status on the data
buffer. Some watermarks are set. As soon as data buffer
is run over the warning threshold, flow control mecha-
nism is triggered to deter the underlying host(s) to trans-
mit frames for sometime. For half-duplex operation port(s),
jam pattern is issued to the attached host. For full-du-
plex operation port(s), specific “pause” frame of IEEE
Std. 802.3x is issued to host. Moreover user can pro-
gram the threshold of broadcast frame storage to dis-
card over-loaded ones to prevent potential of broadcast
storming occurring. After buffer fullness drops in the safe
margin, controller releases flow control state to allow
physical ports to work in norm condition.
Per port utilization information can be retrieved through
serial LED interface. User can program the control regis-
ter for ‘a(chǎn)ll-port ’ display mode or ‘select-port ’ display
mode with 8-bit indication or 5-bit indication.
System manufactures’ design flexibility is our concern
too. MX98206 provides expansion bus interface for 2
MX98206s cascading. Simple bus protocol is utilized to
control traffic transaction on expansion bus. In 16-port
Fast Ethernet switch paradigm, only one EEPROM is
required for auto-configuration. Figure 1 below illustrates
the functional block diagram of MX98206, and Figure 2
depicts the pin assignment of MX98206.
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