參數(shù)資料
型號(hào): MX98207AC
廠商: MACRONIX INTERNATIONAL CO LTD
元件分類: 微控制器/微處理器
英文描述: 12-Port Dual-Speed Ethernet Switch Controller(12端口、雙速以太網(wǎng)開(kāi)關(guān)控制器)
中文描述: 12 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PBGA292
封裝: 27 X 27 MM, BGA-292
文件頁(yè)數(shù): 1/37頁(yè)
文件大?。?/td> 611K
代理商: MX98207AC
1
P/N:PM0660
REV. 0.2, JUN. 23, 2000
MX98207AC
12-Port Dual-Speed Ethernet Switch Controller
FEATURES
Single-chip 12-port 10/100Mbps wire-speed switched
Ethernet controller.
Integration of 12 dual-speed, full/half duplex capable
Media Access Controllers (MACs) with RMII interfaces
Support Store-and-Forward switching scheme.
Support 2.1Gbps (@66MHz) expansion (inter-switch)
bus interface.
Support source/destination MAC address lookup, learn-
ing, and aging within built-in storage of 1K MAC ad-
dress.
Optional MII port in replacement of the cascading in-
terface.
GENERAL DESCRIPTION
The MX98207AC is a 12-port 10/100Mbps single-chip
shared-memory Ethernet switch controller. A desktop or
departmental switched Ethernet solution can be achieved
by combining MX98207AC, the necessary physical de-
vices and low-cost memory. All 12 ports are full-duplex
capable to provide private 20/200Mbps bandwidth con-
nection to power users or servers through external physi-
cal (PHY) layers. System manufacturers can cascade 2
MX98207AC switch controllers to build a 24-port 10/
100Mbps switched Ethernet box easily.
MX98207AC supports store-and-forward switching
scheme with built-in storage of 1K MAC address. The
function modules integrated in controller include 12 full-
duplex capable media access controller with RMII inter-
face to PHYs, address resolution logic (ARL) for MAC
address learning and recognition, queue manager, and
expansion bus interface for 2 MX98207ACs cascading.
It complies fully with IEEE Std. 802.3/802.3u specifica-
tion, and supports MDC/MDIO interface for physical layer
management with industrial standard physical devices.
The flow control mechanism is provided to prevent buffer
overflow that would force controller to lose packets. Con-
troller will monitor the traffic through receive terminal of
each physical port, and frame queuing status on the data
PRELIMINARY
Support IEEE802.3x compliant flow control for FDX
and back-pressure flow control for HDX.
Support up to 2MB SSRAM (pipeline type, or flow
through type) as data buffer.
Serial EEPROM interface for auto-configuration.
Broadcast storm control.
LED interface for utilization indication of each port.
Cascade 2 switch controllers to construct 24 10/
100MBps switched Ethernet ports in a box easily with-
out extra logic.
3.3V COMS technology, package in 292-pin BGA.
buffer. Some watermarks are set. As soon as data buffer
is run over the warning threshold, flow control mecha-
nism is triggered to deter the underlying host(s) to trans-
mit frames for sometime. For half-duplex operation port(s),
jam pattern is issued to the attached host. For full-du-
plex operation port(s), specific "pause" frame of IEEE
Std. 802.3x is issued to the host. Moreover user can
program the threshold of broadcast frame storage to dis-
card over-loaded ones to prevent potential of broadcast
storming. After buffer fullness drops in the safe margin,
controller releases flow control state to allow physical
ports to work in norm condition.
Per port utilization information can be retrieved through
serial LED interface. User can program the control regis-
ter for "all-port" display mode or "select-port" display mode
with 8-bit indication or 5-bit indication.
System manufactures' design flexibility is our concern
too. MX98207AC provides expansion bus interface for 2
MX98207ACs cascading. Simple bus protocol is utilized
to control traffic transaction on expansion bus.
MX98207AC also provides an optional MII port for gen-
eral connection in case no expansion bus is used. Note
that for this configuration, only 11 RMII ports are avail-
able. In 24-port fast Ethernet switch paradigm, only one
EEPROM is required for auto-configuration. Figure 1 and
Figure2 below illustrate the functional block diagrams of
MX98207AC. And Figure3 depicts the pin assignment.
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