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參數(shù)資料
| 型號： | MX97102QC |
| 廠商： | MACRONIX INTERNATIONAL CO LTD |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | MB 6C 6#20 PIN RECP |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 3/42頁 |
| 文件大?。?/td> | 309K |
| 代理商： | MX97102QC |
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3
P/N:PM0473
REV. 2.5, SEP. 05, 2000
MX97102
PIN DESCRIPTION (44-PIN)
TABLE 1: MX97102 PIN DESCRIPTIONS
LQFP
PAD#
37
38
39
40
41
42
43
44
27
28
PLCC
PAD# PIN NAME
41
PAD0(D0)
42
PAD1(D1)
43
PAD2(D2)
44
PAD3(D3)
1
PAD4(D4)
2
PAD5(D5)
3
PAD6(D6)
4
PAD7(D7)
37
PCSN
38
PWRN(R/W)
I
I/O DESCRIPTION
Multiplexed Bus Mode:Address/data bus from the CPU system to this devic
,and data between the CPU system and this device.
Non-Multiplexed Bus Mode:Data bus between the CPU system and this
I/O device.
I
ChipSelect:A logic "LOW" enable this device for a read/write operation.
Read/Write:A logic "HIGH" indicates a valid read operation by CPU.
A logic "LOW" indicates a valid write operation by CPU.(Motorola bus
mode) Write:A logic "LOW" indicates a write operation.(Intel bus mode)
Data Strobe:
The rising edge marks the end of a valid read or write operation (Motorola
bus mode). Read:A logic "LOW" indicates a read operation.(Intel bus mode)
Open Interrupt Request:The signal is a logic "LOW" when this device
requests an Drain interrupt. It is an open drain output.
29
39
PRDN(DS)
I
8
23
PINTN
1~5,
9,13,15
17~20
31~36
45~49
56,60
26
14
19,20
29,30
NC
No used.
36
PALE
I
Address Latch Enable:A logic "HIGH" indicates an address on the address/
data bus(Multiplexed bus type only). ALE also selects the micro-processor
interface type (multiplexed or non-multiplexed).
I/O Reset:A logic "HIGH" on this input forces this device into reset state. The
minimum pulse length is four DCL-clock periods or four ms. If the terminal
specific functions are enabled,this device may also output a reset signal.
O(I) Frame Sync 1:Frame sync output. Logic "HIGH" during channel 0 on the
GCI interface. This pin becomes Input if Test Mode is programmed (register
ADF1).
O(I) Data Clock:Clock of frequency, 1536kHz output, equals to twice the GCI
data rate.
This pin becomes Input if Test Mode is programmed (register ADF1)
O
This pin output the Echo bit from the receiving line.
54
9
PRST
59
13
PFSC1
58
12
PDCL
62
16
ECHO
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