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參數(shù)資料
| 型號： | MT9LD272AG |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 2Meg x 72 Nonbuffered DRAM DIMMs(2M x 72無緩沖動態(tài)RAM雙列直插存儲器模塊) |
| 中文描述： | 2Meg × 72 Nonbuffered內(nèi)存插槽（200萬× 72無緩沖動態(tài)RAM的雙列直插存儲器模塊） |
| 文件頁數(shù)： | 6/30頁 |
| 文件大?。?/td> | 410K |
| 代理商： | MT9LD272AG |
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2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
6
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
OBSOLETE
PIN DESCRIPTIONS
PIN NUMBERS
30, 45
SYMBOL
RAS0#, RAS2#
TYPE
Input
DESCRIPTION
Row-Address Strobe: RAS# is used to clock-in the row-
address bits. Two RAS# inputs allow for one x72 bank or
two x36 banks.
Column-Address Strobe: CAS# is used to clock-in the
column-address bits, enable the DRAM output buffers
and strobe the data inputs on WRITE cycles. Eight CAS#
inputs allow byte access control for any memory bank
configuration.
Write Enable: WE# is the READ/WRITE control for the
DQ pins. If WE# is LOW prior to CAS# going LOW, the
access is an EARLY WRITE cycle. If WE# is HIGH while
CAS# is LOW, the access is a READ cycle, provided OE#
is also LOW. If WE# goes LOW after CAS# goes LOW,
then the cycle is a LATE WRITE cycle. A LATE WRITE
cycle is generally used in conjunction with a READ cycle
to form a READ-MODIFY-WRITE cycle.
Output Enable: OE# is the input/output control for the DQ
pins. These signals may be driven, allowing LATE WRITE
cycles.
Address Inputs: These inputs are multiplexed and clocked
by RAS# and CAS#.
Data I/O: For WRITE cycles, DQ0-DQ63 act as inputs to
the addressed DRAM location. For READ access cycles,
DQ0-DQ63 act as outputs for the addressed DRAM
location.
28, 29, 46, 47, 112,
113, 130, 131
CAS0#-CAS7#
Input
27, 48
WE0#, WE2#
Input
31, 44
OE0#, OE2#
Input
33-38, 117-121
A0-A10
Input
2-5, 7-11, 13-17, 19-20,
55-58, 60, 65-67, 69-72,
74-77, 86-89,91-95,
97-101, 103-104,
139-142, 144, 149-151,
153-156, 158-161
21-22, 52-53, 105-106,
136-137
42, 62, 111, 115,
125-126, 128, 132, 146
6, 18, 26, 40, 41, 49, 59,
73, 84, 90, 102, 110,
124, 133, 143, 157, 168
1, 12, 23, 32, 43, 54, 64,
68, 78, 85, 96, 107, 116,
127, 138, 148, 152, 162
82
DQ0-DQ63
Input/
Output
CB0-CB7
Input/Output
Check Bits.
RFU
–
Reserved for Future Use: These pins should be left
unconnected.
Power Supply: +3.3V
±
0.3V.
V
DD
Supply
V
SS
Supply
Ground.
SDA
Input/Output
Serial Presence-Detect Data. SDA is a bidirectional pin
used to transfer addresses and data into and data out of
the presence-detect portion of the module.
Serial Clock for Presence-Detect. SCL is used to
synchronize the presence-detect data transfer to and
from the module.
Presence-Detect Address Inputs. These pins are used to
configure the presence-detect device.
83
SCL
Input
165-167
SA0-SA2
Input
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PDF描述 |
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| MT9LD272 | 2Meg x 72 Buffered DRAM DIMMs(2M x 72緩沖動態(tài)RAM模塊（雙列直插存儲器模塊）) |
| MT9VDDT1672A | DDR SDRAM DIMM |
| MT9VDDT3272A | DDR SDRAM DIMM |
| MTB2P50E | Power MOSFET 2 Amps, 500 Volts(2A, 500V功率MOSFET) |
| MTB50P03HDL | Power MOSFET 50 Amps, 30 Volts, Logic Level(50A, 30V, D2PAK, P溝道功率MOSFET) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9LD272AG-52B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 Burst EDO Page Mode DRAM Module |
| MT9LD272AG-5X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 EDO Page Mode DRAM Module |
| MT9LD272AG-6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 Fast Page Mode DRAM Module |
| MT9LD272AG-60B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 Burst EDO Page Mode DRAM Module |
| MT9LD272AG-6X | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:2, 4 MEG x 72 NONBUFFERED DRAM DIMMs |
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