參數(shù)資料
型號: MT9LD272AG
廠商: Micron Technology, Inc.
英文描述: 2Meg x 72 Nonbuffered DRAM DIMMs(2M x 72無緩沖動態(tài)RAM雙列直插存儲器模塊)
中文描述: 2Meg × 72 Nonbuffered內(nèi)存插槽(200萬× 72無緩沖動態(tài)RAM的雙列直插存儲器模塊)
文件頁數(shù): 14/30頁
文件大?。?/td> 410K
代理商: MT9LD272AG
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
14
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
OBSOLETE
SERIAL PRESENCE-DETECT EEPROM OPERATING CONDITIONS
(Notes: 1) (V
DD
= +3.3V
±
0.3V)
PARAMETER/CONDITION
SUPPLY VOLTAGE
INPUT HIGH VOLTAGE: Logic 1; All inputs
INPUT LOW VOLTAGE: Logic 0; All inputs
OUTPUT LOW VOLTAGE: I
OUT
= 3mA
INPUT LEAKAGE CURRENT: V
IN
= GND to V
DD
OUTPUT LEAKAGE CURRENT: V
OUT
= GND to V
DD
STANDBY CURRENT:
SCL = SDA = V
DD
- 0.3V; All other inputs = GND or 3.3V +10%
POWER SUPPLY CURRENT:
SCL clock frequency = 100 KHz
SYMBOL
V
DD
V
IH
V
IL
V
OL
I
LI
I
LO
I
SB
MIN
3
MAX
3.6
UNITS
V
V
V
V
μ
A
μ
A
μ
A
NOTES
V
DD
×
0.7 V
DD
+ 0.5
-1
V
DD
×
0.3
0.4
10
10
30
I
CC
2
mA
SERIAL PRESENCE-DETECT EEPROM AC ELECTRICAL CHARACTERISTICS
(Notes: 1) (V
DD
= +3.3V
±
0.3V)
PARAMETER/CONDITION
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
SYMBOL
t
AA
t
BUF
t
DH
t
F
t
HD:DAT
t
HD:STA
t
HIGH
t
I
t
LOW
t
R
t
SCL
t
SU:DAT
t
SU:STA
t
SU:STO
t
WR
MIN
0.3
4.7
300
MAX
3.5
UNITS
μ
s
μ
s
ns
ns
μ
s
μ
s
μ
s
ns
μ
s
μ
s
KHz
ns
μ
s
μ
s
ms
NOTES
300
0
4
4
100
4.7
1
100
250
4.7
4.7
10
28
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