參數(shù)資料
型號： MT93L00A
廠商： Zarlink Semiconductor Inc.
英文描述： Multi-Channel Voice Echo Canceller
中文描述： 多通道語音回聲消除器
文件頁數(shù)： 26/39頁
文件大?。?/td> 636K
代理商： MT93L00A
MT93L00A
Data Sheet
26
Zarlink Semiconductor Inc.
Power Reset Value
48h
7
6
5
4
3
2
1
0
DTDT
15
DTDT
14
DTDT
13
DTDT
12
DTDT
10
DTDT
9
DTDT
8
DTDT
11
Echo Canceller A, Double-Talk Detection Threshold Register 2
Read/Write Address: 15h + Base Address
Echo Canceller B, Double-Talk Detection Threshold Register 2
Read/Write Address: 35h + Base Address
Power Reset Value
00h
7
6
5
4
3
2
1
0
DTDT
7
DTDT
6
DTDT
5
DTDT
4
DTDT
2
DTDT
1
DTDT
0
DTDT
3
Echo Canceller A, Double-Talk Detection Threshold Register 1
Read/Write Address: 14h + Base Address
Echo Canceller B, Double-Talk Detection Threshold Register 1
Read/Write Address: 34h + Base Address
This register allows the user to program the level of Double-Talk Detection Threshold (DTDT). The 16 bit 2’s complement linear
value
defaults
to 4800h= 0.5625 or -5 dB. The maximum value is 7FFFh = 0.9999 or 0 dB. The high byte is in Register 2 and
the low byte is in Register 1.
(DTDT)
(DTDT)
Power Reset Value
0Bh
7
6
5
4
3
2
1
0
NLP
15
NLP
14
NLP
13
NLP
12
NLP
10
NLP
9
NLP
8
NLP
11
Echo Canceller A, Non-Linear Processor Threshold Register 2
Read/Write Address: 19h + Base Address
Echo Canceller B, Non-Linear Processor Threshold Register 2
Read/Write Address: 39h + Base Address
Power Reset Value
60h
7
6
5
4
3
2
1
0
NLP
7
NLP
6
NLP
5
NLP
4
NLP
2
NLP
1
NLP
0
NLP
3
Echo Canceller A, Non-Linear Processor Threshold Register 1
Read/Write Address: 18h + Base Address
Echo Canceller B, Non-Linear Processor Threshold Register 1
Read/Write Address: 38h + Base Address
This register allows the user to program the level of the Non-Linear Processor Threshold (NLPTHR). The 16 bit 2’s complement
linear value
defaults
to 0B60h = 0.0889 or -21.0 dB. The maximum value is 7FFFh = 0.9999 or 0 dB. The high byte is in
Register 2 and the low byte is in Register 1.
(NLPTHR)
(NLPTHR)
Power Reset Value
40h
7
6
5
4
3
2
1
0
MU
15
MU
14
MU
13
MU
12
MU
10
MU
9
MU
8
MU
11
Echo Canceller A, Adaptation Step Size (MU) Register 2
Echo Canceller B, Adaptation Step Size (MU) Register 2
Read/Write Address: 1Bh + Base Address
Read/Write Address: 3Bh + Base Address
Power Reset Value
00h
7
6
5
4
3
2
1
0
MU
7
MU
6
MU
5
MU
4
MU
2
MU
1
MU
0
MU
3
Echo Canceller A, Adaptation Step Size (MU) Register 1
Echo Canceller B, Adaptation Step Size (MU) Register 1
Read/Write Address: 1Ah + Base Address
Read/Write Address: 3Ah + Base Address
This register allows the user to program the level of MU. MU is a 16 bit 2’s complement value which defaults to 4000h = 1.0
The maximum value is 7FFFh or 1.9999 decimal. The high byte is in Register 2 and the low byte is in Register 1.
(MU)
(MU)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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MT93L04 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:128-Channel Voice Echo Canceller
MT93L04A 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:128-Channel Voice Echo Canceller
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