參數(shù)資料
型號: MT93L00A
廠商: Zarlink Semiconductor Inc.
英文描述: Multi-Channel Voice Echo Canceller
中文描述: 多通道語音回聲消除器
文件頁數(shù): 23/39頁
文件大?。?/td> 636K
代理商: MT93L00A
MT93L00A
Data Sheet
23
Zarlink Semiconductor Inc.
Bit
Name
Description
7
res
Reserved bit.
6
TD
Logic high indicates the presence of a 2100 Hz tone.
5
DTDet
Logic high indicates the presence of a double-talk condition.
4
res
Reserved bit.
3
res
Reserved bit.
2
res
Reserved bit.
1
TDG
Tone detection status bit gated with the AutoTD bit.
Logic high indicates that AutoTD has been enabled and the tone detector has
detected the presence of a 2100 Hz tone.
0
NB
Logic high indicates the presence of a narrow-band signal on Rin.
Bit
Name
Description
7-4
res
Reserved bits. Must always be set to zero for normal operation.
3
RingClr
When high, the instability detector is activated. When low, the instability detector is
disabled
2
PathClr
When high, the current echo channel estimate will be cleared and the echo canceller
will enter fast convergence mode upon detection of a path change. When low, the
echo canceller will keep the current path estimate but revert to fast convergence
mode upon detection of a path change. Note: this bit is ignored if PathDet is low.
1
PathDet
When high, the path change detector is activated. When low, the path change
detector is disabled.
0
res
Reserved bit. Must always be set to zero for normal operation.
Echo Canceller A, Status Register
Echo Canceller B, Status Register
NB
TDG
res
res
res
DTDet
TD
res
7
6
5
4
3
2
1
0
Reset Value:
00
H
.
Read Address:
Read Address:
02
H
+ Base Address
22
H
+ Base Address
Echo Canceller A, Control Register A3
Echo Canceller B, Control Register B3
res
PathDet
PathClr
RingClr
res
res
res
res
7
6
5
4
3
2
1
0
Reset Value:
0A
H
.
Read/Write Address: 08
H
+ Base Address
Read/Write Address: 28
H
+ Base Address
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