參數(shù)資料
型號(hào): MT93L00A
廠商: Zarlink Semiconductor Inc.
英文描述: Multi-Channel Voice Echo Canceller
中文描述: 多通道語(yǔ)音回聲消除器
文件頁(yè)數(shù): 17/39頁(yè)
文件大?。?/td> 636K
代理商: MT93L00A
MT93L00A
Data Sheet
17
Zarlink Semiconductor Inc.
Figure 10 - Power Up Sequence Flow Diagram
Power Management
Each group of echo cancellers can be placed in Power Down mode by writing a “0” into the PWUP bit in their
respective Main Control Register. When a given group is in Power Down mode, the corresponding PCM data are
bypassed from Rin to Rout and from Sin to Sout with two frames delay. Refer to the Main Control Register section
for description.
The typical power consumption can be calculated with the following equation:
P
C
= 9 * Nb_of_groups + 3.6, in mW
where 0
Nb_of_groups
16
Call Initialization
To ensure fast initial convergence on a new call, it is important to clear the Adaptive filter. This is done by putting the
echo canceller in bypass mode for at least one frame (125
μ
s) and then enabling adaptation.
System Powerup
Reset Held Low
Delay 100
μ
s
Reset High
MCLK Active
Delay 500
μ
s
Reg. Reset
Software
Hardware
Reset Low
Delay 1000 ns
Reset High
PWUP to “1”
Delay 250
μ
s
PWUP to “0”
Delay 500
μ
s
ECAN Ready
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