參數(shù)資料
型號： MT9162AN1
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 編解碼器
英文描述： 5 Volt Single Rail Codec
中文描述： A/MU-LAW, PROGRAMMABLE CODEC, PDSO20
封裝： 5.30 MM, SSOP-20
文件頁數(shù)： 9/22頁
文件大?。?/td> 568K
代理商： MT9162AN1
MT9162
Data Sheet
9
Zarlink Semiconductor Inc.
AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
AC Characteristics
for A/D (Transmit) Path
- 0dBm0 = A
Lo3.17
- 3.17dB = 1.773V
rms
for
μ
-Law and 0dBm0 = A
Lo3.14
- 3.14dB = 1.843V
rms
for A-Law, at the Codec. (V
Ref
=0.6 volts and V
Bias
=2.5 volts.)
Characteristics
Sym.
Min.
Typ.
Max.
Units
Test Conditions
1
Analog input equivalent to overload
decision
A
Li3.17
A
Li3.14
7.334
7.6
Vp-p
Vp-p
μ
-Law
A-Law
Both at Codec
2
Absolute half-channel gain
AIN
±
to Dout
G
AX1
G
TX
5.2
6.0
6.8
dB
Transmit filter gain=0dB
setting.
@1020Hz
3
Gain tracking vs. input level
ITU-T G.714 Method 2
-0.3
-0.6
-1.6
0.3
0.6
1.6
dB
dB
dB
3 to -40 dBm0
-40 to -50 dBm0
-50 to -55 dBm0
4
Signal to total Distortion vs. input
level.
ITU-T G.714 Method 2
D
QX
35
29
24
dB
dB
dB
0 to -30 dBm0
-40 dBm0
-45 dBm0
5
Transmit Idle Channel Noise
N
CX
N
PX
G
RX
8.5
-71
12
-69
dBrnC0
dBm0p
μ
-Law
A-Law
6
Gain relative to gain at
<50Hz
60Hz
200Hz
300 - 3000 Hz
3000 - 3400 Hz
4000 Hz
>4600 Hz
-0.25
-0.9
-45
-23
-40
-25
-30
0.0
0.25
0.25
-12.5
-25
dB
dB
dB
dB
dB
dB
dB
7
Absolute Delay
D
AX
360
μ
s
at frequency of minimum
delay
8
Group Delay relative to D
AX
D
DX
750
380
130
750
μ
s
μ
s
μ
s
μ
s
500-600 Hz
600 - 1000 Hz
1000 - 2600 Hz
2600 - 2800 Hz
9
Power Supply Rejection
f=1020 Hz
f=0.3 to 3 kHz
f=3 to 4 kHz
f=4 to 50 kHz
PSSR
PSSR1
PSSR2
PSSR3
37
37
40
35
40
dB
dB
dB
dB
±
100mV peak signal on
V
DD
μ
-law
PSSR1-3 not production
tested
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