參數(shù)資料
型號: MT9162AN1
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 編解碼器
英文描述: 5 Volt Single Rail Codec
中文描述: A/MU-LAW, PROGRAMMABLE CODEC, PDSO20
封裝: 5.30 MM, SSOP-20
文件頁數(shù): 11/22頁
文件大?。?/td> 568K
代理商: MT9162AN1
MT9162
Data Sheet
11
Zarlink Semiconductor Inc.
Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
Timing is over recommended temperature range & recommended power supply voltages.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
NOTE 1:Not production tested, guaranteed by design.
Electrical Characteristics
for Analog Inputs
Characteristics
Sym.
Min.
Typ.
Max.
Units
Test Conditions
1
Maximum input voltage without
overloading Codec
across AIN+/AIN-
V
IOLH
2.90
3.00
Vp-p
A/
μ
= 0
A/
μ
= 1
2
Input Impedance
Z
I
50
k
AIN+/AIN- to V
SS
AC Electrical Characteristics
- SSI BUS Synchronous Timing (see Figure 5)
Characteristics
Sym.
Min.
Typ.
Max.
Units
Test Conditions
1
2
3
BCL Clock Period
BCL Pulse Width High
BCL Pulse Width Low
t
BCL
t
BCLH
t
BCLL
t
R
/t
F
t
ENW
t
SSS
t
SSH
t
DOZL
244
1953
ns
ns
ns
ns
ns
ns
ns
ns
BCL=4096 kHz to 512 kHz
BCL=4096 kHz
BCL=4096 kHz
Note 1
Note 1
122
122
20
4
5
6
BCL Rise/Fall Time
Strobe Pulse Width
Strobe setup time before BCL falling
8 x t
BCL
70
80
t
BCL-80
t
BCL
-80
50
7
8
Strobe hold time after BCL falling
Dout High Impedance to Active Low
from Strobe rising
Dout High Impedance to Active High
from Strobe rising
10 Dout Active Low to High Impedance
from Strobe falling
11 Dout Active High to High Impedance
from Strobe falling
12 Dout Delay (high and low) from BCL
rising
13 Din Setup time before BCL falling
14 Din Hold Time from BCL falling
C
L
=150 pF, R
L
=1K
9
t
DOZH
50
ns
C
L
=150 pF, R
L
=1K
t
DOLZ
50
ns
C
L
=150 pF, R
L
=1K
t
DOHZ
50
ns
C
L
=150 pF, R
L
=1K
t
DD
50
ns
C
L
=150 pF, R
L
=1K
t
DIS
t
DIH
20
50
ns
ns
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