- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359233 > MT8966AS (Mitel Networks Corporation) Integrated PCM Filter Codec PDF資料下載
參數(shù)資料
| 型號： | MT8966AS |
| 廠商： | Mitel Networks Corporation |
| 元件分類： | Codec |
| 英文描述： | Integrated PCM Filter Codec |
| 中文描述： | 集成的PCM編解碼器 |
| 文件頁數(shù)： | 5/32頁 |
| 文件大?。?/td> | 607K |
| 代理商： | MT8966AS |
第1頁第2頁第3頁第4頁當(dāng)前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
MT8960/61/62/63/64/65/66/67
Data Sheet
5
Zarlink Semiconductor Inc.
injects this voltage level into the non-inverting input of the comparator. An integrating capacitor (of value between
0.1 and 1
μ
F) must be externally connected from this point (ANUL) to the Analog Ground (GNDA).
The absolute gain of the transmit filter (nominally 0 dB at 1 kHz) can be adjusted from 0 dB to 7 dB in 1 dB steps by
means of three binary controlled gain pads.
The resulting bandpass characteristics with the limits shown in Figure 10 meet the CCITT and AT&T recommended
specifications. Typical attenuations are 30 dB for 0-60 Hz and 35 dB for 4.6 kHz and above.
The filter output signal is an 8 kHz staircase waveform which is fed into the codec capacitor array, or alternatively,
into an external capacitive load of 250 pF when the chip is in the test mode. The digital encoder generates an eight-
bit digital word representation of the 8 kHz sampled analog signal. The first bit of serial data stream is bit 7 (MSB)
and represents the sign of the analog signal. Bits 4-6 represent the chord which contains the analog sample value.
Bits 0-3 represent the step value of the analog sample within the selected chord. The MT8960-63 provide a sign
plus magnitude PCM output code format. The MT8964/66 PCM output code conforms to the AT &T D3
specification, i.e., true sign bit and inverted magnitude bits. The MT8965/67 PCM output code conforms to the
CCITT specifications with alternate digit inversion (even bits inverted). See Figs. 3 and 4 for the digital output code
corresponding to the analog voltage, V
IN
, at V
X
input.
The eight-bit digital word is output at DSTo at a nominal rate of 2.048 MHz, via the output buffer as the first 8-bits of
the 125
μ
s sampling frame.
Receive Path
An eight-bit PCM encoded digital word is received on DSTi input once during the 125
μ
s period and is loaded into
the input register. A charge proportional to the received PCM word appears on the capacitor array and an 8 kHz
sample and hold circuit integrates this charge and holds it for the rest of the sampling period.
The receive (D/A) filter provides interpolation filtering on the 8 kHz sample and hold signal from the codec. The filter
consists of a 3.4 kHz lowpass fifth-order elliptic section clocked at 128 kHz and performs bandlimiting and
smoothing of the 8 kHz "staircase" waveform. In addition, sinx/x gain correction is applied to the signal to
compensate for the attenuation of higher frequencies caused by the capacitive sample and hold circuit. The
absolute gain of the receive filter can be adjusted from 0 dB to -7 dB in 1 dB steps by means of three binary
controlled gain pads. The resulting lowpass characteristics, with the limits shown in Figure 11, meet the CCITT and
AT & T recommended specifications.
Typical attenuation at 4.6 kHz and above is 30 dB. The filter is followed by a buffer amplifier which will drive 5V
peak/peak into a 10k ohm load, suitable for driving electronic 2-4 wire circuits.
V
Ref
An external voltage must be supplied to the V
Ref
pin which provides the reference voltage for the digital encoding
and decoding of the analog signal. For V
Ref
= 2.5 V, the digital encode decision value for overload (maximum
analog signal detect level) is equal to an analog input V
IN
= 2.415 V (
μ
-Law version) or 2.5 V (A-Law version) and is
equivalent to a signal level of 3.17 dBm0 or 3.14 dBm0 respectively, at the codec.
The analog output voltage from the decoder at V
R
is defined as:
μ
-Law:
Ref
X
[(
128
)
+
(
128
)(
33
)]
±
V
-0.5
2
C
16.5 + S
V
OFFSET
A-Law:
V
2
C+1
0.5 + S
Ref
X
[(
128
32
)]
±
V
OFFSET
C=0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT8981DP1 | ISO-CMOS ST-BUS |
| MT8981DPR | ISO-CMOS ST-BUS |
| MT8981DPR1 | ISO-CMOS ST-BUS |
| MT8981D-1 | ISO-CMOS ST-BUS⑩ FAMILY Digital Switch |
| MT8981DE | ISO-CMOS ST-BUS⑩ FAMILY Digital Switch |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT8966AS1 | 制造商:Microsemi Corporation 功能描述: 制造商:Microsemi Corporation 功能描述:PCM FLTR CODEC 20SOIC W - Rail/Tube 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC CODEC U-LAW CCITT PCM 20SOIC 制造商:Microsemi Corporation 功能描述:IC CODEC U-LAW CCITT PCM 20SOIC |
| MT8966ASR1 | 制造商:Microsemi Corporation 功能描述:AUD CODEC 1ADC / 1DAC 20SOIC W - Tape and Reel 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC CODEC U-LAW CCITT PCM 20SOIC 制造商:Microsemi Corporation 功能描述:IC CODEC U-LAW CCITT PCM 20SOIC |
| MT8967 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Integrated PCM Filter Codec |
| MT8967AS | 制造商:Microsemi Corporation 功能描述: |
| MT8967AS1 | 制造商:Microsemi Corporation 功能描述:AUD CODEC 1ADC / 1DAC 20SOIC W - Rail/Tube 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC CODEC A-LAW CCITT PCM 20SOIC 制造商:Microsemi Corporation 功能描述:IC CODEC A-LAW CCITT PCM 20SOIC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。