參數(shù)資料
型號: MT8966AS
廠商: Mitel Networks Corporation
元件分類: Codec
英文描述: Integrated PCM Filter Codec
中文描述: 集成的PCM編解碼器
文件頁數(shù): 1/32頁
文件大?。?/td> 607K
代理商: MT8966AS
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.
Features
ST-BUS
compatible
Transmit/Receive filters & PCM Codec in one I.C
Meets AT&T D3/D4 and CCITT G711 and G712
μ
-Law: MT8960/62/64/67
A-Law: MT8961/63/65/67
Low power consumption:
Op.: 30 mW typ.
Stby.: 2.5 mW typ.
Digital Coding Options:
MT8964/65/66/67 CCITT Code
MT8960/61/62/63 Alternative Code
Digitally controlled gain adjust of both filters
Analog and digital loopback
Filters and codec independently user accessible
for testing
Powerdown mode available
2.048 MHz master clock input
Up to six uncommitted control outputs
±
5 V
±
5% power supply
Description
Manufactured in ISO
2
-CMOS, these integrated
filter/codecs are designed to meet the demanding
performance needs of the digital telecommunications
industry, e.g., PABX, Central Office, Digital telephones.
February 2005
Ordering Information
18 Pin PDIP
20 Pin PDIP
20 Pin SOIC
20 Pin SOIC
18 Pin PDIP*
20 Pin PDIP*
20 Pin SOIC*
20 Pin SOIC*
MT8960/61/64/65AE
MT8962/63AE
MT8962/63/66/67AS
MT8963ASR
MT8960AE1
MT8962/63AE1
MT8962AS1
MT8963AS1
Tubes
Tubes
Tubes
Tape & Reel
Tubes
Tubes
Tubes
Tubes
*Pb Free Matte Tin
-40
°
C to +85
°
C
ISO
2
-CMOS
MT8960/61/62/63/64/65/66/67
Integrated PCM Filter Codec
Data Sheet
Figure 1 - Functional Block Diagram
ANUL
V
X
SD0
SD1
SD2
SD3
SD4
SD5
V
R
V
Ref
GNDA
GNDD
V
DD
V
EE
DSTo
CSTi
CA
F1i
C2i
DSTi
Transmit
Filter
Output
Register
Receive
Filter
Analog to
Digital PCM
Encoder
PCM Digital
to Analog
Decoder
Output
Register
Input
Register
A Register
8-Bits
B-Register
8-Bits
Control
Logic
相關(guān)PDF資料
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