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參數(shù)資料
| 型號： | MT8930C |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Subscriber Network Interface Circuit |
| 中文描述： | 用戶網(wǎng)絡接口電路 |
| 文件頁數(shù)： | 23/41頁 |
| 文件大?。?/td> | 2516K |
| 代理商： | MT8930C |
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Data Sheet
MT8930C
23
Table 14. NT Mode C-channel Diagnostic Register (Write Add. 01000
B
and
B0
= 1)
Table 15. NT Mode Status Register
(2)
(Read Add. 01001
)
Bus activity is set when three zeros are received in a time period equivalent to 48 bits or 250
μ
s. It is reset when 128
consecutive ones are received.
The Status Register is updated internally once every ST-BUS frame. Therefore, more than one read access per frame will
return the same value.
Note 1:
Note 2:
BIT
NAME
DESCRIPTION
B7-B6
Loop
The status of these two bits determine which type of loopback is to be performed:
B7 - B6
0 - 0
- no loopback active
0 - 1
- near end loopback LTx to LRx
1 - 0
- digital loopback DSTi to DSTo
1 - 1
- remote loopback LRx to LTx
B5
FSync
If ’1’, the device will maintain frame synchronization even after losing the framing
sequence (i.e., if the device is transmitting INFO2 or INFO4 and this bit is set, the same
INFO signal will still be transmitted even if the frame sync sequence in the received signal
is lost).
If ’0’, synchronization will be declared when three consecutive framing sequences have
been detected without error.
B4
FLv
If ’1’, the frame sync sequence will violate the bipolar violation encoding rule.
If ’0’, the framing pattern resumes normal operation, i.e., Framing bit is a bipolar violation.
B3
Idle
Setting this bit to ’1’ will force an all 1s signal to be transmitted on the line.
B2
Echo
Setting this bit to ’1’ will force all D-echo bits (E) to zero.
B1
Slave
If ’1’, the device will operate in a NT slave mode. This allows the device to be used at the
terminal equipment end of the line while receiving its clocks from an external source.
B0
RegSel
If the register select bit is set to ’1’, the control register is redefined as the diagnostic
register. A ’0’ gives access to the control register.
BIT
NAME
DESCRIPTION
B7
Sync/BA
This bit is set when the device has achieved frame synchronization while the activation
request is asserted (DR = 0 and AR = 1). If there is a deactivation request or AR is low
(DR = 1 or AR = 0), this bit indicates the presence of bus activity
(1)
.
A bus activity identifies
the reception of INFO frames (INFO1 or INFO3).
B6-B5
IS0-IS1
Binary encoded state sequence.
IS0 - IS1
0 - 0
- deactivated
0 - 1
- pending deactivation
1 - 0
- pending activation
1 - 1
- activated
B4
RxMCH
Following a ‘0’ input at the HALF pin or HALF bit in the C-channel Control Register, the
state of this bit reflects the received maintenance Q-channel (received in the Fa bit position
during multiframing).
This bit will always read ‘1’ if multiframing is not used.
B3-B0
NA
These bits will read
’1’.
相關PDF資料 |
PDF描述 |
|---|---|
| MT8930CE | Subscriber Network Interface Circuit |
| MT8930CP | Subscriber Network Interface Circuit |
| MT8931C | Subscriber Network Interface Circuit |
| MT8931CE | Subscriber Network Interface Circuit |
| MT8931CP | Subscriber Network Interface Circuit |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT8930C-1 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS ST-BUS⑩ FAMILY Subscriber Network Interface Circuit |
| MT8930CC | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS ST-BUS⑩ FAMILY Subscriber Network Interface Circuit Preliminary Information |
| MT8930CE | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Subscriber Network Interface Circuit |
| MT8930CP | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Subscriber Network Interface Circuit |
| MT8930CPR | 制造商:Microsemi Corporation 功能描述: |
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