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參數(shù)資料
| 型號： | MT8930C |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Subscriber Network Interface Circuit |
| 中文描述： | 用戶網(wǎng)絡(luò)接口電路 |
| 文件頁數(shù)： | 10/41頁 |
| 文件大?。?/td> | 2516K |
| 代理商： | MT8930C |
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MT8930C
Data Sheet
10
Figure 7 - Link Activation Protocol, State Diagram
Signals from NT to TE
Signals from TE to NT
Info0
Info2
Info4
No Signal
Valid frame structure with
all B, D, D-echo and A bits
set to ‘0’
Valid frame with data in B,
D, D-echo channels. Bit A is
set to 1.
Info1
and six ‘1’s
(1)
Info3
Valid frame with data in B & D
Bits
Where: BA
(2)
= Bus Activity
DR = Deactivation Request
AR = Activation Request
Sync
(2)
= Frame Sync Signal
A = Activation bit
Time out = 32 ms Timer Signal
Note 1: signal is not timebase locked to NT.
Note 2: Sync/BA bit of the Status Register
is configured as Sync bit when
AR = 1 and DR = 0, or as BA bit
when AR = 0 or DR = 1. A change in
the state of the AR and/or DR bits
will cause a change in the function
of the Sync/BA bit in the following
ST-BUS frame.
TE State Activation Diagram
NT State Activation Diagram
DR = 1
AR = 1
Sync = 1
BA = 0
Sync = 1
DR = 1
DR = 1
BA = 0
A = 1 &
Sync = 1
Sync = 0
A = 0
Activation Request
send Info1 if BA = 0
send Info0 if BA = 1
Deactivated
send Info0
Synchronized
send Info3 if Sync = 1
send Info0 if Sync = 0
Activated
send Info3
BA = 1
AR = 1
BA =0
Time out
DR = 1
AR = 1
Sync = 1
Sync = 0
DR = 1
Deactivated
send Info0
Pending
Activation
send Info2
Pending
Deactivation
Send Info0
Activated
send Info4
Info0
Continuous Signal of +‘0’, -‘0’
Line Wiring Configuration
The MT8930C can interface to any of the three
wiring configurations which are specified by CCITT
Recommendation I.430 and ANSI T1.605 (refer to
Figs. 8 to 10). These consist of a point-to-point or
one of the two point-to-multipoint configurations (i.e.,
short passive bus or the extended passive bus). The
selection of line configurations is performed using
the timing bit (B4 of NT Mode Control Register).
For the short passive bus, TE devices are connected
at random points along the cable. However, for the
extended passive bus all connection points are
grouped at the far end of the cable from the NT.
For an NT SNIC in fixed timing mode, the VCO and
Rx filters/peak detectors are disabled and the
threshold voltage is fixed. However, for a TE SNIC
or an NT SNIC (in adaptive timing mode), the VCO
and Rx filters/peak detectors are enabled. In this
manner, the device can compensate for variable
round trip delays and line attenuation using a
threshold voltage set to a fixed percentage of the
pulse peak amplitude.
Another operation can be implemented using the
SNIC in the star configuration as shown in Figure 14.
This mode allows multiple NTs, with physically
independent S-Busses, to share a common input
source and transfer information down the S-Bus to
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| MT8930CE | Subscriber Network Interface Circuit |
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| MT8931CE | Subscriber Network Interface Circuit |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT8930C-1 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS ST-BUS⑩ FAMILY Subscriber Network Interface Circuit |
| MT8930CC | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS ST-BUS⑩ FAMILY Subscriber Network Interface Circuit Preliminary Information |
| MT8930CE | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Subscriber Network Interface Circuit |
| MT8930CP | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Subscriber Network Interface Circuit |
| MT8930CPR | 制造商:Microsemi Corporation 功能描述: |
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