參數(shù)資料
型號(hào): MT54V512H18E
廠商: Micron Technology, Inc.
英文描述: 512K x 18 Synchronous Pipelined Burst SRAM(9Mb,流水線式,同步脈沖靜態(tài)存儲(chǔ)器)
中文描述: 為512k × 18同步流水線突發(fā)靜態(tài)存儲(chǔ)器(9Mb以上,流水線式,同步脈沖靜態(tài)存儲(chǔ)器)
文件頁(yè)數(shù): 8/22頁(yè)
文件大?。?/td> 260K
代理商: MT54V512H18E
8
512K x 18 2.5V V
DD
, HSTL, QDRb4 SRAM
MT54V512H18E.p65 – Rev. 3/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
ADVANCE
512K x 18
2.5V V
DD
, HSTL, QDRb4 SRAM
BUS CYCLE STATE DIAGRAM
NOTE:
1. The address is concatenated with two additional internal LSBs to facilitate burst operation. The address order is
always fixed as: xxx...xxx+0, xxx...xxx+1, xxx...xxx+2, xxx...xxx+3. Bus cycle is terminated at the end of this sequence
(burst count = 4).
2. State transitions: RD = (R# = LOW); WT = (W# = LOW).
3. Read and write state machines can be active simultaneously. Read and write cannot be simultaneously initiated. Read
takes precedence.
4. State machine control timing is controlled by K.
LOAD NEW
READ ADDRESS;
R_Count=0;
R_Init=1
READ DOUBLE;
R_Count=R_Count+2
INCREMENT READ
R_Init=0
POWER-UP
Supply
voltage
provided
READ PORT NOP
R_Init=0
RD & R_Count=4
RD
R_Count=2
always
always
/RD & R_Count=4
/RD
LOAD NEW
WRITE ADDRESS;
W_Count=0
WRITE DOUBLE;
W_Count=W_Count+2
INCREMENT WRITE
Supply
voltage
provided
WRITE PORT NOP
WT & W_Count=4
WT & R_Init=0
W_Count=2
always
always
/WT
/WT & W_Count=4
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PDF描述
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