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參數(shù)資料
| 型號： | MT54V512H18E |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 512K x 18 Synchronous Pipelined Burst SRAM(9Mb，流水線式，同步脈沖靜態(tài)存儲器) |
| 中文描述： | 為512k × 18同步流水線突發(fā)靜態(tài)存儲器（9Mb以上，流水線式，同步脈沖靜態(tài)存儲器） |
| 文件頁數(shù)： | 2/22頁 |
| 文件大?。?/td> | 260K |
| 代理商： | MT54V512H18E |
2
512K x 18 2.5V V
DD
, HSTL, QDRb4 SRAM
MT54V512H18E.p65 – Rev. 3/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
ADVANCE
512K x 18
2.5V V
DD
, HSTL, QDRb4 SRAM
NOTE:
1. The functional block diagram illustrates simplified device operation. See truth table, pin descriptions and timing
diagrams for detailed information.
2. n = 17
All synchronous data outputs pass through output
registers controlled by the rising edges of the output
clocks (C and C# if provided, otherwise K and K#).
Four pins are used to implement JTAG test capabili-
ties: test mode select (TMS), test data-in (TDI), test clock
(TCK) and test data-out (TDO). JTAG circuitry is used to
serially shift data to and from the SRAM. JTAG inputs
use JEDEC-standard 2.5V I/O levels to shift data during
this testing mode of operation.
The SRAM operates from a +2.5V power supply, and
all inputs and outputs are HSTL-compatible. The device
is ideally suited for applications that benefit from a
high-speed fully-utilized DDR data bus.
Please refer to Micron’s Web site (www.micron.com/
mti/msp/html/sramprod.html) for the latest data sheet.
READ/WRITE OPERATIONS
All bus transactions operate on an uninterruptable
burst of four data, requiring two full clock cycles of bus
utilization. Any request that attempts to interrupt a
burst in progress is ignored. The resulting benefit is that
the address rate is kept down to the clock frequency
even when both buses are 100 percent utilized.
READ cycles are pipelined. The request is initiated
by asserting R# LOW at K rising edge. Data is delivered
GENERAL DESCRIPTION (continued)
after the next rising edge of K using C and C# as the
output timing references, or using K and K# if C and C#
are tied HIGH. If C and C# are tied HIGH, they may not
be toggled during device operation. Output tri-stating
is automatically controlled such that the bus is released
if no data is being delivered. This permits banked SRAM
systems with no complex OE timing generation. Back-
to-back READ cycles are initiated every second K rising
edge. Any command in between is ignored, since the
burst sequence may not be interrupted and requires
two full clock cycles.
WRITE cycles are initiated by W# LOW at K rising
edge. Data is expected at both rising edges of K andK#
beginning one clock period later. Write registers are
incorporated to facilitate pipelined self-timed WRITE
cycles and provide fully coherent data for all combina-
tions of READs and WRITEs. A READ can immediately
follow a WRITE even if they are to the same address.
Although the WRITE data has not been written to the
memory array, the SRAM will deliver the data from the
Write Register instead of using the older data from the
memory array. The latest data is always utilized for all
bus transactions. WRITE cycles are initiated every sec-
ond K rising edge. Any command in between is ignored,
since the burst sequence may not be interrupted.
FUNCTIONAL BLOCK DIAGRAM
512K x 18
ADDRESS
D (Data In)
n
n
R#
W#
K
18
36
36
36
36
72
K#
K
R#
W#
BW0#
BW1#
K
2 x 72
MEMORY
ARRAY
C
ADDRESS
REGISTRY
& LOGIC
DATA
REGISTRY
& LOGIC
C,C#
18
Q
(Data Out)
R
E
G
W
R
I
T
E
MUX
MUX
D
R
I
V
E
R
W
R
I
T
E
O
U
T
P
U
T
O
U
T
P
U
T
R
E
G
B
U
F
F
E
R
A
M
P
S
S
E
N
S
E
O
U
T
P
U
T
S
E
L
E
C
T
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT54V512H18E1F-5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT54V512H18EF-10 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT54V512H18EF-6 | 制造商:Cypress Semiconductor 功能描述:DS2KX18 SRAM PLASTIC FBGA 2.5V 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT54V512H18EF-6C | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT54V512H36EF-5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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