- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385640 > MT54V512H18A (Micron Technology, Inc.) 512K x 18 Synchronous Pipelined Burst SRAM(9Mb，流水線式，同步脈沖靜態(tài)存儲器) PDF資料下載
參數(shù)資料
| 型號： | MT54V512H18A |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 512K x 18 Synchronous Pipelined Burst SRAM(9Mb，流水線式，同步脈沖靜態(tài)存儲器) |
| 中文描述： | 為512k × 18同步流水線突發(fā)靜態(tài)存儲器（9Mb以上，流水線式，同步脈沖靜態(tài)存儲器） |
| 文件頁數(shù)： | 9/22頁 |
| 文件大?。?/td> | 258K |
| 代理商： | MT54V512H18A |
9
512K x 18 2.5V V
DD
, HSTL, QDRb2 SRAM
MT54V512H18A.p65 – Rev. 3/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
ADVANCE
512K x 18
2.5V V
DD
, HSTL, QDRb2 SRAM
NOTE:
1. X means “ Don’t Care.” H means logic HIGH. L means logic LOW.
-
means rising edge;
ˉ
means falling edge.
2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges except if C
and C# are HIGH then data outputs are delivered at K and K# rising edges.
3. R# and W# must meet setup/hold times around the rising edge (LOW to HIGH) of K and are registered at the rising
edge of K.
4. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. It is recommended that K = /K# = C = /C# when clock is stopped. This is not essential but permits most rapid restart by
overcoming transmission line charging symmetrically.
7. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST WRITE operation
provided that the setup and hold requirements are satisfied.
BY TE WRITE OPERATION
7
OPERATION
K
K#
BW0#
BW1#
WRITE D0-17 at K rising edge
WRITE D0-17 at K# rising edge
WRITE D0-8 at K rising edge
WRITE D0-8 at K# rising edge
WRITE D9-17 at K rising edge
WRITE D9-17 at K# rising edge
WRITE nothing at K rising edge
WRITE nothing at K# rising edge
L
H
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
L
H
L
H
L
H
L
H
L
H
L
H
L
H
TRUTH TABLE
(Notes 1-6)
OPERATION
K
R#
W#
D OR Q
D OR Q
WRITE Cycle:
Load address, input write data on
consecutive K and K# rising edges
READ Cycle:
Load address, output data on
consecutive C AND C# rising edges
NOP: No operation
L
H
X
L
D
A
(A+0)
at
K(t)
-
Q
A
(A+0)
at
C(t+1)
-
D = X
Q = High-Z
Previous
State
D
A
(A+1)
at
K#(t)
-
Q
A
(A+1)
at
C#(t+1)
-
D = X
Q = High-Z
Previous
State
L
H
L
X
L
H
H
H
STANDBY: Clock stopped
Stopped
X
X
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT54V512H18E | 512K x 18 Synchronous Pipelined Burst SRAM(9Mb，流水線式，同步脈沖靜態(tài)存儲器) |
| MT55L1MY18P | 16Mb: 1 Meg x 18, Flow-Through ZBT SRAM(16Mb流通式同步靜態(tài)存儲器) |
| MT55V1MV18P | 16Mb: 1 Meg x 18, Flow-Through ZBT SRAM(16Mb流通式同步靜態(tài)存儲器) |
| MT55L512L18F | 8Mb: 512K x 18,Flow-Through ZBT SRAM(8Mb流通式同步靜態(tài)存儲器) |
| MT55L256L32F | 8Mb: 256K x 32，F(xiàn)low-Through ZBT SRAM(8Mb流通式同步靜態(tài)存儲器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT54V512H18AF-10 | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 2.5V 9M-Bit 512K x 18 3ns 165-Pin FBGA |
| MT54V512H18AF-7.5 | 制造商:Rochester Electronics LLC 功能描述:- Trays |
| MT54V512H18E1F-5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT54V512H18EF-10 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT54V512H18EF-6 | 制造商:Cypress Semiconductor 功能描述:DS2KX18 SRAM PLASTIC FBGA 2.5V 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。