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參數(shù)資料
| 型號(hào)： | MT54V512H18A |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 512K x 18 Synchronous Pipelined Burst SRAM(9Mb，流水線式，同步脈沖靜態(tài)存儲(chǔ)器) |
| 中文描述： | 為512k × 18同步流水線突發(fā)靜態(tài)存儲(chǔ)器（9Mb以上，流水線式，同步脈沖靜態(tài)存儲(chǔ)器） |
| 文件頁(yè)數(shù)： | 3/22頁(yè) |
| 文件大?。?/td> | 258K |
| 代理商： | MT54V512H18A |
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3
512K x 18 2.5V V
DD
, HSTL, QDRb2 SRAM
MT54V512H18A.p65 – Rev. 3/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
ADVANCE
512K x 18
2.5V V
DD
, HSTL, QDRb2 SRAM
PROGRAMMABLE IMPEDANCE OUTPUT
BUFFER
The QDR SRAM is equipped with programmable
impedance output buffers. This allows a user to match
the driver impedance to the system. To adjust the
impedance, an external precision resistor (RQ) is con-
nected between the ZQ pin and V
SS
. The value of the
resistor must be five times the desired impedance. For
example, a 350
W
resistor is required for an output
impedance of 70
W
. To ensure that output impedance is
one fifth the value of RQ (within 10 percent), the range
of RQ is 175
W
to 350
W
. Alternately, the ZQ pin can be
connected directly to V
DD
, which will place the device
in a minimum impedance mode.
Output impedance updates may be required because
variations may occur in supply voltage and tempera-
ture over time. The device samples the value of RQ. An
update of the impedance is transparent to the system.
Impedance updates do not affect device operation, and
all data sheet timing and current specifications are met
during an update.
The device will power up with an output impedance
set at 50
W
. To guarantee optimum output driver imped-
ance after power-up, the SRAM needs 1,024 cycles to
update the impedance. The user can operate the part
with fewer than 1,024 clock cycles, but optimal output
impedance is not guaranteed.
Vt
Vt = V
REF
Vt
C C#
ZQ
Q0-17
K
K#
D0-17
SA
C C#
ZQ
Q0-17
K
K#
D0-17
SA
BUS
MASTER
(CPU
or
ASIC)
SRAM #1
SRAM #4
DATA IN 0-71
DATA OUT 0-71
Address 0-17
Read#
Write#
BW0-7#
Return CLK
Source CLK
Return CLK#
Source CLK#
R=50
R=250
R=250
R
#
W
#
B
W
0
#
B
W
1
#
R
#
W
#
B
W
0
#
B
W
1
#
Vt
Vt
Vt
R
R
APPLICATION EXAMPLE
CLOCK CONSIDERATIONS
The device does not utilize internal phase-locked
loops and can therefore be placed into a stopped-clock
state to minimize power without lengthy restart times.
It is strongly recommended that the clocks operate for
a number of cycles prior to initiating commands to the
SRAM. This delay permits transmission line charging
effects to be overcome and allows the clock timing to be
nearer to its steady-state value.
SINGLE CLOCK MODE
The SRAM can be used with the single K, K# clock
pair by tying C and C# HIGH. In this mode the SRAM
will use K and K# in place of C and C#. This mode
provides the most rapid data output but does not
compensate for system clock skew and flight times.
DEPTH EXPANSION
Port select inputs are provided for the read and write
ports. This allows for easy depth expansion. Both Port
Selects are sampled on the rising edge of K only. Each
port can be independently selected and deselected and
do not affect the operation of the opposite port. All
pending transactions are completed prior to a port
deselecting.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT54V512H18AF-10 | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 2.5V 9M-Bit 512K x 18 3ns 165-Pin FBGA |
| MT54V512H18AF-7.5 | 制造商:Rochester Electronics LLC 功能描述:- Trays |
| MT54V512H18E1F-5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT54V512H18EF-10 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT54V512H18EF-6 | 制造商:Cypress Semiconductor 功能描述:DS2KX18 SRAM PLASTIC FBGA 2.5V 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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