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參數(shù)資料
| 型號(hào)： | MT54V512H18A |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 512K x 18 Synchronous Pipelined Burst SRAM(9Mb，流水線式，同步脈沖靜態(tài)存儲(chǔ)器) |
| 中文描述： | 為512k × 18同步流水線突發(fā)靜態(tài)存儲(chǔ)器（9Mb以上，流水線式，同步脈沖靜態(tài)存儲(chǔ)器） |
| 文件頁數(shù)： | 2/22頁 |
| 文件大小： | 258K |
| 代理商： | MT54V512H18A |
2
512K x 18 2.5V V
DD
, HSTL, QDRb2 SRAM
MT54V512H18A.p65 – Rev. 3/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
ADVANCE
512K x 18
2.5V V
DD
, HSTL, QDRb2 SRAM
NOTE:
1. The functional block diagram illustrates simplified device operation. See truth table, pin descriptions and timing
diagrams for detailed information.
2. n = 18
the highest address. All synchronous data outputs pass
through output registers controlled by the rising edges
of the output clocks (C and C# if provided, otherwise K
and K#).
Four pins are used to implement JTAG test capabili-
ties: test mode select (TMS), test data-in (TDI), test clock
(TCK) and test data-out (TDO). JTAG circuitry is used to
serially shift data to and from the SRAM. JTAG inputs
use JEDEC-standard 2.5V I/O levels to shift data during
this testing mode of operation.
The SRAM operates from a +2.5V power supply, and
all inputs and outputs are HSTL-compatible. The device
is ideally suited for applications that benefit from a
high-speed fully-utilized DDR data bus.
Please refer to Micron’s Web site (www.micron.com/
mti/msp/html/sramprod.html) for the latest data sheet.
READ/WRITE OPERATIONS
All bus transactions operate on an uninterruptable
burst of two data, requiring one full clock cycle of bus
utilization.The resulting benefit is that short data trans-
actions can remain in operation on both buses pro-
vided that the address rate can be maintained by the
system (2x the clock frequency).
READ cycles are pipelined. The request is initiated
by asserting R# LOW at K rising edge. Data is delivered
after the next rising edge of K using C and C# as the
output timing references, or using K and K# if C and C#
GENERAL DESCRIPTION (continued)
are tied HIGH. If C and C# are tied HIGH, they may not
be toggled during device operation. Output tri-stating
is automatically controlled such that the bus is released
if no data is being delivered. This permits banked SRAM
systems with no complex OE timing generation. Back-
to-back READ cycles are initiated every K rising edge.
WRITE cycles are initiated by W# LOW at K rising
edge. The address for the WRITE cycle is provided at the
following K# rising edge. Data is expected at the rising
edge of K and K# beginning at the same K which
initiated the cycle. Write registers are incorporated to
facilitate pipelined self-timed WRITE cycles and pro-
vide fully coherent data for all combinations of READs
and WRITEs. A READ can immediately follow a WRITE
even if they are to the same address. Although the
WRITE data has not been written to the memory array,
the SRAM will deliver the data from the Write Register
instead of using the older data from the memory array.
The latest data is always utilized for all bus transactions.
WRITE cycles can be initiated on every K rising edge.
BY TE WRITE OPERATIONS
BYTE WRITE operations are supported. The active
LOW byte write controls, BW0# and BW1#, are regis-
tered coincident with their corresponding data.
This feature can eliminate the need for some READ/
MODIFY/WRITE cycles, collapsing it to a single BYTE
WRITE operation in some instances.
FUNCTIONAL BLOCK DIAGRAM
512K x 18
ADDRESS
D (Data In)
n
n
R#
W#
K
K#
18
36
36
36
K#
K
R#
W#
BW0#
BW1#
K
2 x 36
MEMORY
ARRAY
C
ADDRESS
REGISTRY
& LOGIC
DATA
REGISTRY
& LOGIC
C,C#
18
Q
(Data Out)
R
E
G
W
R
I
T
E
MUX
D
R
I
V
E
R
W
R
I
T
E
O
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T
P
U
T
O
U
T
P
U
T
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G
B
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F
F
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A
M
P
S
S
E
N
S
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U
T
P
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T
S
E
L
E
C
T
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT54V512H18AF-10 | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 2.5V 9M-Bit 512K x 18 3ns 165-Pin FBGA |
| MT54V512H18AF-7.5 | 制造商:Rochester Electronics LLC 功能描述:- Trays |
| MT54V512H18E1F-5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT54V512H18EF-10 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT54V512H18EF-6 | 制造商:Cypress Semiconductor 功能描述:DS2KX18 SRAM PLASTIC FBGA 2.5V 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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