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參數(shù)資料
| 型號(hào)： | MT49H8M36HU-33 |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 8M X 36 DDR DRAM, 0.3 ns, PBGA144 |
| 封裝： | FBGA-144 |
| 文件頁(yè)數(shù)： | 56/76頁(yè) |
| 文件大?。?/td> | 2659K |
| 代理商： | MT49H8M36HU-33 |
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PDF: 09005aef80a41b59/Source: 09005aef809f284b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
288Mb_RLDRAM_II_CIO_D2.fm - Rev N 5/08 EN
6
2003 Micron Technology, Inc. All rights reserved.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
General Description
The Micron reduced latency DRAM (RLDRAM) II is a high-speed memory device
designed for high bandwidth data storage—telecommunications, networking, and
cache applications, etc. The chip’s 8-bank architecture is optimized for sustainable high
speed operation.
The DDR I/O interface transfers two data words per clock cycle at the I/O balls. Output
data is referenced to the free-running output data clock.
Commands, addresses, and control signals are registered at every positive edge of the
differential input clock, while input data is registered at both positive and negative edges
of the input data clock(s).
Read and write accesses to the RLDRAM are burst-oriented. The burst length (BL) is
programmable from 2, 4, or 8 by setting the mode register.
The device is supplied with 2.5V and 1.8V for the core and 1.5V or 1.8V for the output
drivers.
Bank-scheduled refresh is supported with the row address generated internally.
The BGA 144-ball package is used to enable ultra high-speed data transfer rates and a
simple upgrade path from early generation devices.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT49H8M36HU-33 IT | 制造商:Micron Technology Inc 功能描述: |
| MT49H8M36HU-5 | 制造商:Micron Technology Inc 功能描述: |
| MT4A5 | 制造商:EDAL 制造商全稱(chēng):EDAL 功能描述:SILICON FAST RECOVERY 3.0 AMP DIODES |
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