參數(shù)資料
型號: MT49H32M9CFM-xx
廠商: Micron Technology, Inc.
英文描述: 288Mb SIO REDUCED LATENCY(RLDRAM II)
中文描述: 288Mb二氧化硅約化延遲(延遲DRAM二)
文件頁數(shù): 6/44頁
文件大?。?/td> 1117K
代理商: MT49H32M9CFM-XX
16 MEG x 18, 32 MEG x 9
2.5V V
EXT
, 1.8V V
DD
, HSTL, SIO, RLDRAM II
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
6
Figure 2: Functional Block Diagram – 16 Meg x 18
NOTE:
1. When the BL = 8 setting is used, A18 and A19 are “Don’t Care.“
2. When BL = 4 setting is used, A19 is “Don’t Care.”
A0–A19
1, 2
, B0, B1, B2
Column Address
Buffer
Column Address
Counter
Refresh
Counter
Row Decoder
Memory Array
Bank 1
C
S
Row Address
Buffer
Row Decoder
Memory Array
Bank 0
C
S
Row Decoder
Memory Array
Bank 2
C
S
Row Decoder
Memory Array
Bank 3
C
S
Row Decoder
Memory Array
Bank 5
C
S
Row Decoder
Memory Array
Bank 4
C
S
Row Decoder
Memory Array
Bank 6
C
S
Row Decoder
Memory Array
Bank 7
C
C
C
D
D
W
C
R
D
V
R
S
Output Data Valid
QVLD
Output Data Clock
QK[1:0], QK#[1:0]
Input Buffers
Output Buffers
Control Logic and Timing Generator
D0–D17
Q0–Q17
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