參數(shù)資料
型號(hào): MT49H32M9CFM-xx
廠商: Micron Technology, Inc.
英文描述: 288Mb SIO REDUCED LATENCY(RLDRAM II)
中文描述: 288Mb二氧化硅約化延遲(延遲DRAM二)
文件頁(yè)數(shù): 33/44頁(yè)
文件大?。?/td> 1117K
代理商: MT49H32M9CFM-XX
16 MEG x 18, 32 MEG x 9
2.5V V
EXT
, 1.8V V
DD
, HSTL, SIO, RLDRAM II
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
33
Configuration Table
In this mode, the READ and WRITE latencies are
increased by one clock cycle. The RLDRAM cycle time
remains the same, as described in Table 11.
NOTE:
1. BL = 8 is not available for configuration 1.
Refresh Command in Multiplexed
Address Mode
Similar to other commands, the refresh command is
executed on the next rising clock edge when in the
multiplexed address mode. However, since only bank
address is required for AREF, the next command can be
applied on the following clock. The operation of the
AREF command and any other command is repre-
sented in Figure 35.
Figure 35: Burst Refresh Operation
NOTE:
AREF: AUTO REFRESH
AC: Any command
A
x
: First part A
x
of address
A
y
: Second part A
y
of address
BA
k
: Bank
k
;
k
is chosen so that
t
RC is met
Table 11:
Configuration Table In Multiplexed Address Mode
CONFIGURATION
FREQUENCY
SYMBOL
1
1
4
2
6
3
8
UNIT
cycles
t
RC
t
RL
t
WL
t
RC
t
RL
t
WL
t
RC
t
RL
t
WL
t
RC
t
RL
t
WL
5
7
9
cycles
6
8
10
cycles
400 MHz
20.0
ns
22.5
ns
25.0
ns
300 MHz
20.0
26.7
ns
23.3
30.0
ns
26.7
33.3
ns
200 MHz
20.0
30.0
40.0
ns
25.0
35.0
45.0
ns
35.0
40.0
50.0
ns
ADDR
CK#
CK
CMD
0
1
2
3
4
5
6
7
8
AC
AREF
AREF
AREF
AREF
AREF
AREF
AREF
DON’T CARE
AREF
9
10
Ax
Ay
AC
Ax
Ay
11
BADDR
BAk
BA0
BA1
BA2
BA3
BA4
BA5
BA6
BA7
BAk
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