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參數(shù)資料
| 型號(hào)： | MT49H32M9CFM-xx |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 288Mb SIO REDUCED LATENCY(RLDRAM II) |
| 中文描述： | 288Mb二氧化硅約化延遲（延遲DRAM二） |
| 文件頁數(shù)： | 5/44頁 |
| 文件大小： | 1117K |
| 代理商： | MT49H32M9CFM-XX |
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16 MEG x 18, 32 MEG x 9
2.5V V
EXT
, 1.8V V
DD
, HSTL, SIO, RLDRAM II
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
5
General Description
The Micron
288Mb reduced latency DRAM
(RLDRAM) II is a high-speed memory device designed
for high bandwidth communication data storage.
Applications include, but are not limited to, transmit-
ting or receiving buffers in telecommunication sys-
tems and data or instruction cache applications
requiring large amounts of memory. The chip's eight-
bank architecture is optimized for high speed and
achieves a peak bandwidth of 28.8 Gb/s, using two
separate 18-bit double data rate (DDR) parts and a
maximum system clock of 400 MHz.
The DDR separate I/O interface transfers two 18- or
9-bit wide data word per clock cycle at the I/O balls.
The read port has dedicated data outputs to support
READ operations, while the write port has dedicated
input balls to support WRITE operations. Output data
is referenced to the free-running output data clock.
This architecture eliminates the need for high-speed
bus turnaround.
Commands, addresses, and control signals are reg-
istered at every positive edge of the differential input
clock, while input data is registered at both positive
and negative edges of the input data clock(s).
Read and write accesses to the RLDRAM are burst-
oriented. The burst length is programmable from 2, 4,
or 8 by setting the mode register.
The device is supplied with 2.5V and 1.8V for the
core and 1.5V or 1.8V for the output drivers.
Bank-scheduled refresh is supported with row
address generated internally.
A standard FBGA 144-ball package is used to enable
ultra high-speed data transfer rates and a simple
upgrade path from former products.
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| MT4C1004J | 4 Meg x 1 FPM DRAM(4 M x 1快速頁面模式動(dòng)態(tài)RAM) |
| MT4C4001STG-6 | standard or self refresh |
| MT4C4001STG-7 | standard or self refresh |
| MT4C4001STG-8 | standard or self refresh |
| MT4C4001JDJ-6 | standard or self refresh |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT49H32M9CHU-25 | 制造商:Micron Technology Inc 功能描述:DRAM CHIP RLDRAM 288MBIT 1.8V 144FBGA - Trays |
| MT49H32M9CHU-33 | 制造商:Micron Technology Inc 功能描述:32MX9 RLDRAM PLASTIC FBGA 1.8V SEPARATE I/O 8 BANKS 1.8V I/O - Trays |
| MT49H32M9CHU-5 | 制造商:Micron Technology Inc 功能描述:32MX9 RLDRAM PLASTIC FBGA 1.8V SEPARATE I/O 8 BANKS 1.8V I/O - Trays |
| MT49H32M9FM-25 | 制造商:Micron Technology Inc 功能描述: |
| MT49H32M9FM-25 TR | 功能描述:IC RLDRAM 288MBIT 400MHZ 144FBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 產(chǎn)品變化通告:Product Discontinuation 05/Nov/2008 標(biāo)準(zhǔn)包裝:84 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步 ZBT 存儲(chǔ)容量:4.5M（128K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:119-BGA 供應(yīng)商設(shè)備封裝:119-PBGA（14x22） 包裝:托盤 其它名稱:71V3557SA75BGI |
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