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| 型號： | MT48V16M16LFFG |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | MOBILE SDRAM |
| 中文描述： | 移動SDRAM |
| 文件頁數(shù)： | 19/58頁 |
| 文件大小： | 1451K |
| 代理商： | MT48V16M16LFFG |
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19
256Mb: x16 Mobile SDRAM
MobileRamY26L_A.p65 – Pub. 5/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
256Mb: x16
MOBILE SDRAM
ADVANCE
Figure 11
READ to PRECHARGE
A fixed-length READ burst may be followed by, or
truncated with, a PRECHARGE command to the same
bank (provided that auto precharge was not acti-
vated), and a full-page burst may be truncated with a
PRECHARGE command to the same bank. The
PRECHARGE command should be issued
x
cycles be-
fore the clock edge at which the last desired data ele-
ment is valid, where
x
equals the CAS latency minus
one. This is shown in Figure 11 for each possible CAS
latency; data element
n
+ 3 is either the last of a burst of
four or the last desired of a longer burst. Following the
PRECHARGE command, a subsequent command to
the same bank cannot be issued until
t
RP is met. Note
that part of the row precharge time is hidden during
the access of the last data element(s).
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
NOP
D
OUT
n
+ 1
D
OUT
n
+ 2
D
OUT
n
+ 3
PRECHARGE
ACTIVE
tRP
T7
NOTE:
DQM is LOW.
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
NOP
D
OUT
n
+ 1
D
OUT
n
+ 2
D
OUT
n
+ 3
PRECHARGE
ACTIVE
tRP
T7
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
BANK
a
,
COL
n
NOP
D
OUT
n
+ 1
D
OUT
n
+ 2
D
OUT
n
+ 3
PRECHARGE
ACTIVE
tRP
T7
BANK
a
,
ROW
or all)
(
a
DON’T CARE
X
= 0 cycles
CAS Latency = 1
X
= 1 cycle
CAS Latency = 2
CAS Latency = 3
BANK
a
,
COL
n
BANK
a
,
ROW
BANK
(
a
or all)
BANK
a
,
COL
n
BANK
a
,
ROW
BANK
(
a
or all)
X
= 2 cycles
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