- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384755 > MT48LC4M32LFFC (Micron Technology, Inc.) SYNCHRONOUS DRAM PDF資料下載
參數(shù)資料
| 型號： | MT48LC4M32LFFC |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | SYNCHRONOUS DRAM |
| 中文描述： | 同步DRAM |
| 文件頁數(shù)： | 2/52頁 |
| 文件大?。?/td> | 1281K |
| 代理商： | MT48LC4M32LFFC |
第1頁當(dāng)前第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
2
128Mb: x32 SDRAM
128MbSDRAMx32_D.p65 – Rev. D; Pub. 6/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
128Mb: x32
SDRAM
The SDRAM provides for programmable READ or
WRITE burst lengths of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst se-
quence.
The 128Mb SDRAM uses an internal pipelined ar-
chitecture to achieve high-speed operation. This ar-
chitecture is compatible with the 2
n
rule of prefetch
architectures, but it also allows the column address to
be changed on every clock cycle to achieve a high-
speed, fully random access. Precharging one bank
while accessing one of the other three banks will hide
the precharge cycles and provide seamless, high-
speed, random-access operation.
The 128Mb SDRAM is designed to operate in 3.3V,
low-power memory systems. An auto refresh mode is
provided, along with a power-saving, power-down
mode. All inputs and outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM oper-
ating performance, including the ability to synchro-
nously burst data at a high data rate with automatic
column-address generation, the ability to interleave
between internal banks to hide precharge time and
the capability to randomly change column addresses
on each clock cycle during a burst access.
GENERAL DESCRIPTION
The 128Mb SDRAM is a high-speed CMOS, dynamic
random-access memory containing 134,217,728-bits.
It is internally configured as a quad-bank DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Each of the
33,554,432-bit banks is organized as 4,096 rows by 256
columns by 32 bits.
Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and con-
tinue for a programmed number of locations in a pro-
grammed sequence. Accesses begin with the registra-
tion of an ACTIVE command, which is then followed by
a READ or WRITE command. The address bits regis-
tered coincident with the ACTIVE command are used
to select the bank and row to be accessed (BA0, BA1
select the bank, A0–A11 select the row). The address
bits registered coincident with the READ or WRITE com-
mand are used to select the starting column location
for the burst access.
128Mb (x32) SDRAM PART NUMBER
PART NUMBER
MT48LC4M32B2TG
ARCHITECTURE
4 Meg x 32
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT48LC64M8A2 | SYNCHRONOUS DRAM |
| MT48LC32M16A2 | SYNCHRONOUS DRAM |
| MT48LC8M16A2FB-75LIT | SYNCHRONOUS DRAM |
| MT48LC8M16A2FB-7E | SYNCHRONOUS DRAM |
| MT48LC8M16A2FB-7EIT | SYNCHRONOUS DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT48LC4M32LFFC-10-REFURB | 制造商:Micron Technology Inc 功能描述: |
| MT48LC4M4A1 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:SYNCHRONOUS DRAM |
| MT48LC4M4A1TGS | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:SYNCHRONOUS DRAM |
| MT48LC4M4A2 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:SYNCHRONOUS DRAM |
| MT48LC64M4A2 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:SYNCHRONOUS DRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。