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參數(shù)資料
| 型號： | MT48LC4M32LFFC |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | SYNCHRONOUS DRAM |
| 中文描述： | 同步DRAM |
| 文件頁數(shù)： | 14/52頁 |
| 文件大?。?/td> | 1281K |
| 代理商： | MT48LC4M32LFFC |
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14
128Mb: x32 SDRAM
128MbSDRAMx32_D.p65 – Rev. D; Pub. 6/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
128Mb: x32
SDRAM
Upon completion of a burst, assuming no other com-
mands have been initiated, the DQs will go High-Z. A
full-page burst will continue until terminated. (At the
end of the page, it will wrap to column 0 and continue.)
Data from any READ burst may be truncated with a
subsequent READ command, and data from a fixed-
length READ burst may be immediately followed by
data from a READ command. In either case, a continu-
ous flow of data can be maintained. The first data ele-
ment from the new burst follows either the last element
of a completed burst or the last desired data element of
a longer burst that is being truncated. The new READ
command should be issued
x
cycles before the clock
edge at which the last desired data element is valid,
where
x
equals the CAS latency minus one. This is shown
in Figure 7 for CAS latencies of one, two and three; data
READs
READ bursts are initiated with a READ command,
as shown in Figure 5.
The starting column and bank addresses are pro-
vided with the READ command, and auto precharge is
either enabled or disabled for that burst access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the ge-
neric READ commands used in the following illustra-
tions, auto precharge is disabled.
During READ bursts, the valid data-out element
from the starting column address will be available fol-
lowing the CAS latency after the READ command. Each
subsequent data-out element will be valid by the next
positive clock edge. Figure 6 shows general timing for
each possible CAS latency setting.
Figure 5
READ Command
Figure 6
CAS Latency
CLK
DQ
T2
T1
T3
T0
CAS Latency = 3
LZ
D
OUT
tOH
t
COMMAND
NOP
READ
tAC
NOP
T4
NOP
DON’T CARE
UNDEFINED
CLK
DQ
T2
T1
T0
CAS Latency = 1
LZ
D
OUT
tOH
t
COMMAND
NOP
READ
tAC
CLK
DQ
T2
T1
T3
T0
CAS Latency = 2
LZ
D
OUT
tOH
t
COMMAND
NOP
READ
tAC
NOP
CS#
WE#
CAS#
RAS#
CKE
CLK
COLUMN
ADDRESS
A0-A7
A10
BA0,1
HIGH
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
BANK
ADDRESS
A8, A9, A11
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