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參數(shù)資料
| 型號： | MT48LC4M32LFFC |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | SYNCHRONOUS DRAM |
| 中文描述： | 同步DRAM |
| 文件頁數(shù)： | 18/52頁 |
| 文件大?。?/td> | 1281K |
| 代理商： | MT48LC4M32LFFC |
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18
128Mb: x32 SDRAM
128MbSDRAMx32_D.p65 – Rev. D; Pub. 6/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
128Mb: x32
SDRAM
Figure 11
READ to PRECHARGE
A fixed-length READ burst may be followed by, or
truncated with, a PRECHARGE command to the same
bank (provided that auto precharge was not acti-
vated), and a full-page burst may be truncated with a
PRECHARGE command to the same bank. The
PRECHARGE command should be issued
x
cycles be-
fore the clock edge at which the last desired data ele-
ment is valid, where
x
equals the CAS latency minus
one. This is shown in Figure 11 for each possible CAS
latency; data element
n
+ 3 is either the last of a burst of
four or the last desired of a longer burst. Following the
PRECHARGE command, a subsequent command to
the same bank cannot be issued until
t
RP is met. Note
that part of the row precharge time is hidden during
the access of the last data element(s).
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
NOP
D
OUT
n
+ 1
D
OUT
n
+ 2
D
OUT
n
+ 3
PRECHARGE
ACTIVE
tRP
T7
NOTE:
DQM is LOW.
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
NOP
D
OUT
n
+ 1
D
OUT
n
+ 2
D
OUT
n
+ 3
PRECHARGE
ACTIVE
tRP
T7
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
BANK
a
,
COL
n
NOP
D
OUT
n
+ 1
D
OUT
n
+ 2
D
OUT
n
+ 3
PRECHARGE
ACTIVE
tRP
T7
BANK
a
,
ROW
BANK
(
a
or all)
DON’T CARE
X
= 0 cycles
CAS Latency = 1
X
= 1 cycle
CAS Latency = 2
CAS Latency = 3
BANK
a
,
COL
n
BANK
a
,
ROW
BANK
(
a
or all)
BANK
a
,
COL
n
BANK
a
,
ROW
BANK
(
a
or all)
X
= 2 cycles
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