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參數(shù)資料
| 型號： | MT48H16M16LFBF-10IT |
| 元件分類： | DRAM |
| 英文描述： | 16M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54 |
| 封裝： | 8 X 9 MM, PLASTIC, VFBGA-54 |
| 文件頁數(shù)： | 9/20頁 |
| 文件大?。?/td> | 314K |
| 代理商： | MT48H16M16LFBF-10IT |
09005aef8175ed0d/09005aef8175ed22
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb Mobile SDR SDRAM_2.fm - Ver. A 11/05 EN
17
2004 Micron Technology, Inc. All rights reserved.
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
Electrical Specifications
Preview
Table 9:
IDD Specifications and Conditions (x32)
Notes: 3, 4, 12, 18, 19, 28, 29; notes appear on pages 19
Parameter/Condition
Symbol
Max
Unit
Notes
-75
-8
-10
Operating one bank active-precharge current:
tRFC = tRFC (MIN); tCK = tCK (MIN);CKE is HIGH;
CS is HIGH between valid commands; Address inputs are switching;
Data bus inputs are stable
IDD1
65
60
55
mA
3, 18, 19,
28
mA
Precharge power-down standby current:
All banks idle, CKE is LOW; CS is HIGH, tCK = tCK (MIN); Address and
control inputs are switching; Data bus inputs are stable
IDD2P
500
A
Precharge power-down standby current with clock stopped:
All banks idle; CKE is LOW; CS is HIGH, CK = LOW;
Address and control inputs are switching; Data bus inputs are
stable
IDD2PS
500
A
Precharge non-power-down standby current:
All banks idle CKE = HIGH; CS = HIGH; tCK = tCK (MIN);
Address and control inputs are switching; Data bus inputs are
stable
IDD2N
15
10
mA
28
Precharge non-power-down standby current: clock stopped
All banks idle, CKE = HIGH; CS = HIGH; CK = LOW;
Address and control inputs are switching; Data bus inputs are
stable
IDD2NS
55
5
mA
Active power-down standby current:
One bank active, CKE = LOW; CS = HIGH; tCK = tCK (MIN);
Address and control inputs are switching; Data bus inputs are
stable
IDD3P
55
5
mA
Active power-down standby current: clock stopped
One bank active, CKE = LOW; CS = HIGH; CK = LOW;
Address and control inputs are switching; Data bus inputs are
stable
IDD3PS
33
3
mA
Active non-power-down standby:
One bank active, CKE = HIGH; CS = HIGH; tCK = tCK (MIN);
Address and control inputs are switching; Data bus inputs are
stable
IDD3N
20
15
mA
Active non-power-down standby: clock stopped
One bank active, CKE = HIGH; CS = HIGH; CK = LOW;
Address and control inputs are switching; Data bus inputs are
stable
IDD3NS
10
mA
3, 12, 19,
28
Operating burst read:
One bank active; BL = 4; CL = 3; tCK = tCK (MIN); Continuous read
bursts; IOUT = 0mA; Address inputs are switching; 50% data
changing each burst
IDD4R
120
115
110
mA
3, 18, 19,
28
Operating burst write:
One bank active; BL = 4; tCK = tCK (MIN); continuous WRITE bursts;
Address inputs are switching; 50% data changing each burst
IDD4W
120
115
110
mA
3, 18, 19,
28
Auto refresh:
Burst refresh; CKE = HIGH
Address and control inputs are switching; Data
bus inputs are stable
tRFC = tRFC (MIN)
IDD5
55
50
45
mA
3, 12, 18,
19, 28, 29
tRFC = 7.8125s
IDD5a
33
3
mA
Deep power-down
Izz
10
A
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相關代理商/技術參數(shù) |
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|---|---|
| MT48H16M16LFBF-75 | 制造商:Micron Technology Inc 功能描述:MICMT48H16M16LFBF-75 IT:G 256MB MOBILE S |
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