參數(shù)資料
型號(hào)： MT48H16M16LFBF-10IT
元件分類： DRAM
英文描述： 16M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54
封裝： 8 X 9 MM, PLASTIC, VFBGA-54
文件頁(yè)數(shù)： 13/20頁(yè)
文件大?。?/td> 314K
代理商： MT48H16M16LFBF-10IT
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
Preview: This data sheet contains initial descriptions of products still under development.This data sheet contains minimum
and maximum limits specified over the complete power supply and temperature range for production devices. Although
considered final, these specifications are subject to change, as further product development and data characterization
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
Notes
09005aef8175ed0d/09005aef8175ed22
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb Mobile SDR SDRAM_2.fm - Ver. A 11/05 EN
20
2004 Micron Technology, Inc. All rights reserved.
Preview
23. The clock frequency must remain constant (stable clock is defined as a signal cycling
within timing constraints specified for the clock pin) during access or precharge
states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be
used to reduce the data rate.
24. Auto precharge mode only. The precharge timing budget (tRP) begins at 7ns for -8
after the first clock delay, after the last WRITE is executed. May not exceed limit set for
precharge mode.
25. Precharge mode only.
26. JEDEC specifies three clocks.
27. Parameter guaranteed by design.
28. For -10, CL = 3 and tCK =10ns.
29. CKE is HIGH during refresh command period tRFC (MIN) else CKE is LOW. The IDD6
limit is actually a nominal value and does not result in a fail value.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT48H16M16LFBF-75 制造商:Micron Technology Inc 功能描述:MICMT48H16M16LFBF-75 IT:G 256MB MOBILE S
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