參數(shù)資料
型號(hào): MT46V4M16
廠商: Micron Technology, Inc.
英文描述: 1 Meg x 16 x 4 banks DDR SDRAM(1M x 16 x 4組,雙數(shù)據(jù)速率同步動(dòng)態(tài)RAM)
中文描述: 1梅格× 16 × 4銀行DDR SDRAM內(nèi)存(100萬× 16 × 4組,雙數(shù)據(jù)速率同步動(dòng)態(tài)RAM)的
文件頁數(shù): 40/69頁
文件大小: 2369K
代理商: MT46V4M16
40
64Mb: x4, x8, x16 DDR SDRAM
64Mx4x8x16DDR_B.p65
Rev. B; Pub. 10/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
64Mb: x4, x8, x16
DDR SDRAM
NOTE (continued):
5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be
applied on each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when
t
RC is met.
Once
t
RC is met, the DDR SDRAM will be in the all banks idle state.
Accessing Mode
Register: Starts with registration of a LOAD MODE REGISTER command and ends when
t
MRD
has been met. Once
t
MRD is met, the DDR SDRAM will be in the all banks idle state.
Precharging All: Starts with registration of a PRECHARGE ALL command and ends when
t
RP is met.
Once
t
RP is met, all banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle, and bursts are not in progress.
8. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ burst, regardless of bank.
10. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or
WRITEs with auto precharge disabled.
11. Requires appropriate DM masking.
12. A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMINATE must be used to
end the READ burst prior to asserting a WRITE command.
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