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| 型號： | MT46V4M16 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 1 Meg x 16 x 4 banks DDR SDRAM(1M x 16 x 4組，雙數(shù)據(jù)速率同步動態(tài)RAM) |
| 中文描述： | 1梅格× 16 × 4銀行DDR SDRAM內(nèi)存（100萬× 16 × 4組，雙數(shù)據(jù)速率同步動態(tài)RAM）的 |
| 文件頁數(shù)： | 15/69頁 |
| 文件大小： | 2369K |
| 代理商： | MT46V4M16 |
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15
64Mb: x4, x8, x16 DDR SDRAM
64Mx4x8x16DDR_B.p65
–
Rev. B; Pub. 10/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
64Mb: x4, x8, x16
DDR SDRAM
AUTO REFRESH
AUTO REFRESH is used during normal operation
of the DDR SDRAM and is analogous to CAS#-BE-
FORE-RAS# (CBR) REFRESH in FPM/EDO DRAMs.
This command is nonpersistent, so it must be issued
each time a refresh is required.
The addressing is generated by the internal refresh
controller. This makes the address bits a “Don’t Care”
during an AUTO REFRESH command. The 64Mb DDR
SDRAM requires AUTO REFRESH cycles at an average
interval of 15.625μs (maximum).
To allow for improved efficiency in scheduling and
switching between tasks, some flexibility in the abso-
lute refresh interval is provided. A maximum of eight
AUTO REFRESH commands can be posted to any
given DDR SDRAM, meaning that the maximum abso-
lute interval between any AUTO REFRESH command
and the next AUTO REFRESH command is 9 × 15.6μs
(140.6μs). This maximum absolute interval is to allow
future support for DLL updates internal to the DDR
SDRAM to be restricted to AUTO REFRESH cycles,
without allowing excessive drift in
t
AC between up-
dates. Although not a JEDEC requirement, to provide
for future functionality features, CKE must be active
(High) during the AUTO REFRESH period. The AUTO
REFRESH period begins when the AUTO REFRESH
command is registered and ends
t
RFC latter.
SELF REFRESH
The SELF REFRESH command can be used to retain
data in the DDR SDRAM, even if the rest of the system
is powered down. When in the self refresh mode, the
DDR SDRAM retains data without external clocking.
The SELF REFRESH command is initiated like an AUTO
REFRESH command except CKE is disabled (LOW).
The DLL is automatically disabled upon entering SELF
REFRESH and is automatically enabled upon exiting
SELF REFRESH (200 clock cycles must then occur before
a READ command can be issued). Input signals except
CKE are “Don’t Care” during SELF REFRESH.
The procedure for exiting self refresh requires a
sequence of commands. First, CK must be stable prior
to CKE going back HIGH. Once CKE is HIGH, the DDR
SDRAM must have NOP commands issued for
t
XSNR
because time is required for the completion of any
internal refresh in progress. A simple algorithm for
meeting both refresh and DLL requirements is to apply
NOPs for 200 clock cycles before applying any other
command.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT46V4M32 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V4M32LG | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V64M16 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE (DDR) SDRAM |
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