參數(shù)資料
型號: MT46V16M4
廠商: Micron Technology, Inc.
英文描述: 4 Meg x 4 x 4 banks DDR SDRAM(4 M x 4 x 4組,雙數(shù)據(jù)速率同步動態(tài)RAM)
中文描述: 4梅格× 4 × 4銀行DDR SDRAM內(nèi)存(四米× 4 × 4組,雙數(shù)據(jù)速率同步動態(tài)RAM)的
文件頁數(shù): 57/69頁
文件大?。?/td> 2369K
代理商: MT46V16M4
57
64Mb: x4, x8, x16 DDR SDRAM
64Mx4x8x16DDR_B.p65
Rev. B; Pub. 10/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
64Mb: x4, x8, x16
DDR SDRAM
Figure 27A
x16 Data Output Timing –
t
DQSQ,
t
QH and Data Valid Window
DQ (Last data valid)
2
DQ
2
DQ
2
DQ
2
DQ
2
DQ
2
DQ
2
LDQS
1
DQ (Last data valid)
2
DQ (First data no longer valid)
2
DQ (First data no longer valid)
2
DQ0 - DQ7 and LDQS, collectively
6
NOTE: 1. DQs transitioning after DQS transition define tDQSQ
window. LDQS defines the lower byte and
UDQS defines the upper byte.
2. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.
3. tDQSQ is derived at each DQS clock edge and is not
cumulative over time and begins with DQS transiti 7. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15.
and ends with the last valid transition of DQs .
T2
T2
T2
T2n
T2n
T2n
T3
T3
T3
T3n
T3n
T3n
CK
CK#
T1
T2
T3
T4
T2n
T3n
tQH
4
tQH
4
tDQSQ
3
tDQSQ
3
tDQSQ
3
tDQSQ
3
Data Valid
window
tDQSQ
3
Data Valid
window
tDQSQ
3
DQ (Last data valid)
7
DQ
7
DQ
7
DQ
7
DQ
7
DQ
7
DQ
7
UDQS
1
DQ (Last data valid)
7
DQ (First data no longer valid)
7
DQ (First data no longer valid)
7
DQ8 - DQ15 and UDQS, collectively
6
T2
T2
T2
T2n
T2n
T2n
T3
T3
T3
T3n
T3n
T3n
tQH
4
tQH
4
tQH
4
tQH
4
tDQSQ
3
tDQSQ
3
tDQSQA
tHP
5
tHP
5
tHP
5
tHP
5
tHP
5
tHP
5
tQH
4
tQH
4
Data Valid
window
Data Valid
window
Data Valid
window
Data Valid
window
Data Valid
window
4. tQH is derived from tHP: tQH = tHP - tQHS.
5. tHP is the lesser of tCL or tCH clock transition
collectively when a bank is active.
6. The data valid window is derived for each
DQS transition and is tQH minus tDQSQ.
U
L
Data Valid
window
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT46V16M8 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM