![](http://datasheet.mmic.net.cn/390000/MT46V16M4_datasheet_16823558/MT46V16M4_22.png)
22
64Mb: x4, x8, x16 DDR SDRAM
64Mx4x8x16DDR_B.p65
–
Rev. B; Pub. 10/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
64Mb: x4, x8, x16
DDR SDRAM
Data from any READ burst may be truncated with
a BURST TERMINATE command, as shown in Figure
11. The BURST TERMINATE latency is equal to the
READ (CAS) latency, i.e., the BURST TERMINATE
command should be issued
x
cycles after the READ
command, where
x
equals the number of desired data
element pairs (pairs are required by the 2
n
-prefetch
architecture).
Data from any READ burst must be completed or
truncated before a subsequent WRITE command can
be issued. If truncation is necessary, the BURST TERMI-
NATE command must be used, as shown in Figure 12.
The
t
DQSS (MIN) case is shown; the
t
DQSS (MAX) case
has a longer bus idle time. (
t
DQSS [MIN] and
t
DQSS
[MAX] are defined in the section on WRITEs.)
A READ burst may be followed by, or truncated
with, a PRECHARGE command to the same bank
provided that auto precharge was not activated. The
PRECHARGE command should be issued
x
cycles after
the READ command, where
x
equals the number of
desired data element pairs (pairs are required by the 2
n
-
prefetch architecture). This is shown in Figure 13.
Following the PRECHARGE command, a subsequent
command to the same bank cannot be issued until
t
RP
is met. Note that part of the row precharge time is
hidden during the access of the last data elements.
READs (continued)