參數(shù)資料
型號: MT46V16M4
廠商: Micron Technology, Inc.
英文描述: 4 Meg x 4 x 4 banks DDR SDRAM(4 M x 4 x 4組,雙數(shù)據(jù)速率同步動態(tài)RAM)
中文描述: 4梅格× 4 × 4銀行DDR SDRAM內(nèi)存(四米× 4 × 4組,雙數(shù)據(jù)速率同步動態(tài)RAM)的
文件頁數(shù): 22/69頁
文件大?。?/td> 2369K
代理商: MT46V16M4
22
64Mb: x4, x8, x16 DDR SDRAM
64Mx4x8x16DDR_B.p65
Rev. B; Pub. 10/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
64Mb: x4, x8, x16
DDR SDRAM
Data from any READ burst may be truncated with
a BURST TERMINATE command, as shown in Figure
11. The BURST TERMINATE latency is equal to the
READ (CAS) latency, i.e., the BURST TERMINATE
command should be issued
x
cycles after the READ
command, where
x
equals the number of desired data
element pairs (pairs are required by the 2
n
-prefetch
architecture).
Data from any READ burst must be completed or
truncated before a subsequent WRITE command can
be issued. If truncation is necessary, the BURST TERMI-
NATE command must be used, as shown in Figure 12.
The
t
DQSS (MIN) case is shown; the
t
DQSS (MAX) case
has a longer bus idle time. (
t
DQSS [MIN] and
t
DQSS
[MAX] are defined in the section on WRITEs.)
A READ burst may be followed by, or truncated
with, a PRECHARGE command to the same bank
provided that auto precharge was not activated. The
PRECHARGE command should be issued
x
cycles after
the READ command, where
x
equals the number of
desired data element pairs (pairs are required by the 2
n
-
prefetch architecture). This is shown in Figure 13.
Following the PRECHARGE command, a subsequent
command to the same bank cannot be issued until
t
RP
is met. Note that part of the row precharge time is
hidden during the access of the last data elements.
READs (continued)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT46V16M8 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM